ai-agent-book/chapter3/structured-index/validation/runs/20260729T200642Z-3_7-4d2d5f9c/evidence.json

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    "publisher": "Intel Corporation",
    "url": "https://cdrdv2.intel.com/v1/dl/getContent/671436",
    "title": "Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 1: Basic Architecture",
    "order_number_revision": "253665-092US",
    "publication": "June 2026",
    "pdf_path": "/Users/boj/book/ai-agent-book/chapter3/structured-index/data/intel-sdm-volume-1.pdf",
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    "cover_metadata_text": "                        Intel® 64 and IA-32 Architectures\n                            Software Developer’s Manual\n                                                                           Volume 1:\n                                                                   Basic Architecture\n\n\n\n\nNOTE: The Intel® 64 and IA-32 Architectures Software Developer's Manual consists of ten volumes:\nBasic Architecture, Order Number 253665; Instruction Set Reference, A-L, Order Number 253666;\nInstruction Set Reference, M-U, Order Number 253667; Instruction Set Reference, V, Order Number\n326018; Instruction Set Reference, W-Z, Order Number 334569; System Programming Guide, Part 1,\nOrder Number 253668; System Programming Guide, Part 2, Order Number 253669; System\nProgramming Guide, Part 3, Order Number 326019; System Programming Guide, Part 4, Order Number\n332831; Model-Specific Registers, Order Number 335592. Refer to all ten volumes when evaluating\nyour design needs.\n\n\n\n\n                                                                  Order Number: 253665-092US\n                                                                                    June 2026\n\f",
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      {
        "page": 254,
        "id": "physical-page-254",
        "text": "PROGRAMMING WITH INTEL® STREAMING SIMD EXTENSIONS (INTEL® SSE)\n\n\nIntel SSE is fully compatible with all software written for IA-32 processors. All existing software continues to run\ncorrectly, without modification, on processors that incorporate Intel SSE. Enhancements to CPUID permit detection\nof Intel SSE. Intel SSE is accessible from all IA-32 execution modes: protected mode, real address mode, and\nvirtual-8086 mode.\nThe following sections of this chapter describe the programming environment for Intel SSE, including: XMM regis-\nters, the packed single precision floating-point data type, and Intel SSE instructions. For additional information,\nsee:\n•   Section 11.6, “Writing Applications with Intel® SSE and SSE2.”\n•   Section 11.5, “Intel® SSE, SSE2, and SSE3 Exceptions,” describes the exceptions that can be generated with\n    Intel SSE/SSE2/SSE3 instructions.\n•   The Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volumes 2A, 2B, 2C, & 2D, provides a\n    detailed description of these instructions.\n•   Chapter 16, “System Programming for Instruction Set Extensions and Processor Extended States,” in the Intel®\n    64 and IA-32 Architectures Software Developer’s Manual, Volume 3A, gives guidelines for integrating these\n    extensions into an operating-system environment.\n\n\n\n10.2          INTEL® SSE PROGRAMMING ENVIRONMENT\nFigure 10-1 shows the execution environment for Intel SSE. All Intel SSE instructions operate on the XMM regis-\nters, MMX registers, and/or memory as follows:\n•   XMM registers — These eight registers (see Figure 10-2 and Section 10.2.2, “XMM Registers”) are used to\n    operate on packed or scalar single precision floating-point data. Scalar operations are operations performed on\n    individual (unpacked) single precision floating-point values stored in the low doubleword of an XMM register.\n    XMM registers are referenced by the names XMM0 through XMM7.\n\n\n                                                                                 Address Space\n                                                                            32\n                                       XMM Registers                    2        -1\n                                        Eight 128-Bit\n\n\n                                 MXCSR Register           32 Bits\n\n\n\n                                                   MMX Registers\n                                                    Eight 64-Bit\n\n\n\n\n                                                      General-Purpose\n                                                         Registers\n                                                        Eight 32-Bit\n\n                                                                                 0\n                                 EFLAGS Register           32 Bits\n\n\n                                  Figure 10-1. Intel® SSE Execution Environment\n\n•   MXCSR register — This 32-bit register (see Figure 10-3 and Section 10.2.3, “MXCSR Control and Status\n    Register”) provides status and control bits used in SIMD floating-point operations.\n•   MMX registers — These eight registers (see Figure 9-2) are used to perform operations on 64-bit packed\n    integer data. They are also used to hold operands for some operations performed between the MMX and XMM\n    registers. MMX registers are referenced by the names MM0 through MM7.\n•   General-purpose registers — The eight general-purpose registers (see Figure 3-5) are used along with the\n    existing IA-32 addressing modes to address operands in memory. (MMX and XMM registers cannot be used to\n\n\n10-2 Vol. 1"
      },
      {
        "page": 255,
        "id": "physical-page-255",
        "text": "PROGRAMMING WITH INTEL® STREAMING SIMD EXTENSIONS (INTEL® SSE)\n\n\n    address memory). The general-purpose registers are also used to hold operands for some SSE instructions and\n    are referenced as EAX, EBX, ECX, EDX, EBP, ESI, EDI, and ESP.\n•   EFLAGS register — This 32-bit register (see Figure 3-7) is used to record result of some compare operations.\n\n\n\n10.2.1      Intel® SSE in 64-Bit Mode and Compatibility Mode\nIn compatibility mode, Intel SSE functions like it does in protected mode. In 64-bit mode, eight additional XMM\nregisters are accessible. Registers XMM8-XMM15 are accessed by using REX prefixes. Memory operands are spec-\nified using the ModR/M, SIB encoding described in Section 3.7.5.\nSome Intel SSE instructions may be used to operate on general-purpose registers. Use the REX.W prefix to access\n64-bit general-purpose registers. Note that if a REX prefix is used when it has no meaning, the prefix is ignored.\n\n\n\n10.2.2      XMM Registers\nEight 128-bit XMM data registers were introduced into the IA-32 architecture with Intel SSE (see Figure 10-2).\nThese registers can be accessed directly using the names XMM0 to XMM7; and they can be accessed independently\nfrom the x87 FPU and MMX registers and the general-purpose registers (that is, they are not aliased to any other\nof the processor’s registers).\n\n\n                         127                                                            0\n                                                       XMM7\n\n                                                       XMM6\n\n                                                       XMM5\n\n                                                       XMM4\n\n                                                       XMM3\n\n                                                       XMM2\n\n                                                       XMM1\n\n                                                       XMM0\n\n\n                                           Figure 10-2. XMM Registers\n\nIntel SSE instructions use the XMM registers only to operate on packed single precision floating-point operands.\nSSE2 extensions expand the functions of the XMM registers to operand on packed or scalar double precision\nfloating-point operands and packed integer operands; see Section 11.2, “Intel® SSE2 Programming Environment,”\nand Section 12.1, “Programming Environment and Data types.”\nXMM registers can only be used to perform calculations on data; they cannot be used to address memory.\nAddressing memory is accomplished by using the general-purpose registers.\nData can be loaded into XMM registers or written from the registers to memory in 32-bit, 64-bit, and 128-bit incre-\nments. When storing the entire contents of an XMM register in memory (128-bit store), the data is stored in 16\nconsecutive bytes, with the low-order byte of the register being stored in the first byte in memory.\n\n\n\n10.2.3      MXCSR Control and Status Register\nThe 32-bit MXCSR register (see Figure 10-3) contains control and status information for Intel SSE, SSE2, and SSE3\nSIMD floating-point operations. This register contains:\n•   Flag and mask bits for SIMD floating-point exceptions.\n•   Rounding control field for SIMD floating-point operations.\n\n\n                                                                                                         Vol. 1 10-3"
      },
      {
        "page": 256,
        "id": "physical-page-256",
        "text": "PROGRAMMING WITH INTEL® STREAMING SIMD EXTENSIONS (INTEL® SSE)\n\n\n•   Flush-to-zero flag that provides a means of controlling underflow conditions on SIMD floating-point operations.\n•   Denormals-are-zeros flag that controls how SIMD floating-point instructions handle denormal source operands.\nThe contents of this register can be loaded from memory with the LDMXCSR and FXRSTOR instructions and stored\nin memory with STMXCSR and FXSAVE.\nBits 16 through 31 of the MXCSR register are reserved and are cleared on a power-up or reset of the processor;\nattempting to write a non-zero value to these bits, using either the FXRSTOR or LDMXCSR instructions, will result\nin a general-protection exception (#GP) being generated.\n\n\n                                    31                                 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0\n\n                                                                          F\n                                                                          T   R   P U O Z D I D P U O Z D I\n                                                 Reserved                                     A\n                                                                          Z   C   M M M M M M   E E E E E E\n                                                                                              Z\n\n\n\n                      Flush to Zero\n                      Rounding Control\n                      Precision Mask\n                      Underflow Mask\n                      Overflow Mask\n                      Divide-by-Zero Mask\n                      Denormal Operation Mask\n                      Invalid Operation Mask\n                      Denormals Are Zeros*\n                      Precision Flag\n                      Underflow Flag\n                      Overflow Flag\n                      Divide-by-Zero Flag\n                      Denormal Flag\n                      Invalid Operation Flag\n                      * The denormals-are-zeros flag was introduced in the Pentium 4 and Intel Xeon processor.\n\n                                         Figure 10-3. MXCSR Control/Status Register\n\n\n10.2.3.1      SIMD Floating-Point Mask and Flag Bits\nBits 0 through 5 of the MXCSR register indicate whether a SIMD floating-point exception has been detected. They\nare “sticky” flags. That is, after a flag is set, it remains set until explicitly cleared. To clear these flags, use the\nLDMXCSR or the FXRSTOR instruction to write zeroes to them.\nBits 7 through 12 provide individual mask bits for the SIMD floating-point exceptions. An exception type is masked\nif the corresponding mask bit is set, and it is unmasked if the bit is clear. These mask bits are set upon a power-up\nor reset. This causes all SIMD floating-point exceptions to be initially masked.\nIf LDMXCSR or FXRSTOR clears a mask bit and sets the corresponding exception flag bit, a SIMD floating-point\nexception will not be generated as a result of this change. The unmasked exception will be generated only upon the\nexecution of the next SSE/SSE2/SSE3 instruction that detects the unmasked exception condition.\nFor more information about the use of the SIMD floating-point exception mask and flag bits, see Section 11.5,\n“Intel® SSE, SSE2, and SSE3 Exceptions,” and Section 12.8, “Intel® SSE3, SSSE3, And Intel® SSE4 Exceptions.”\n\n\n10.2.3.2      SIMD Floating-Point Rounding Control Field\nBits 13 and 14 of the MXCSR register (the rounding control [RC] field) control how the results of SIMD floating-point\ninstructions are rounded. See Section 4.8.4, “Rounding,” for a description of the function and encoding of the\nrounding control bits.\n\n\n10.2.3.3      Flush-To-Zero\nBit 15 (FTZ) of the MXCSR register enables the flush-to-zero mode, which controls the masked response to a SIMD\nfloating-point underflow condition. When the underflow exception is masked and the flush-to-zero mode is\nenabled, the processor performs the following operations when it detects a floating-point underflow condition.\n\n\n10-4 Vol. 1"
      },
      {
        "page": 257,
        "id": "physical-page-257",
        "text": "PROGRAMMING WITH INTEL® STREAMING SIMD EXTENSIONS (INTEL® SSE)\n\n\n•   Returns a zero result with the sign of the true result.\n•   Sets the precision and underflow exception flags.\nIf the underflow exception is not masked, the flush-to-zero bit is ignored.\nThe flush-to-zero mode is not compatible with IEEE Standard 754. The IEEE-mandated masked response to under-\nflow is to deliver the denormalized result (see Section 4.8.3.2, “Normalized and Denormalized Finite Numbers”).\nThe flush-to-zero mode is provided primarily for performance reasons. At the cost of a slight precision loss, faster\nexecution can be achieved for applications where underflows are common and rounding the underflow result to\nzero can be tolerated.\nThe flush-to-zero bit is cleared upon a power-up or reset of the processor, disabling the flush-to-zero mode.\n\n\n10.2.3.4     Denormals-Are-Zeros\nBit 6 (DAZ) of the MXCSR register enables the denormals-are-zeros mode, which controls the processor’s response\nto a SIMD floating-point denormal operand condition. When the denormals-are-zeros flag is set, the processor\nconverts all denormal source operands to a zero with the sign of the original operand before performing any\ncomputations on them. The processor does not set the denormal-operand exception flag (DE), regardless of the\nsetting of the denormal-operand exception mask bit (DM); and it does not generate a denormal-operand exception\nif the exception is unmasked.\nThe denormals-are-zeros mode is not compatible with IEEE Standard 754 (see Section 4.8.3.2, “Normalized and\nDenormalized Finite Numbers”). The denormals-are-zeros mode is provided to improve processor performance for\napplications such as streaming media processing, where rounding a denormal operand to zero does not appre-\nciably affect the quality of the processed data.\nThe denormals-are-zeros flag is cleared upon a power-up or reset of the processor, disabling the denormals-are-\nzeros mode.\nThe denormals-are-zeros mode was introduced in the Pentium 4 and Intel Xeon processor with the SSE2 exten-\nsions; however, it is fully compatible with the SSE SIMD floating-point instructions (that is, the denormals-are-\nzeros flag affects the operation of the SSE SIMD floating-point instructions). In earlier IA-32 processors and in\nsome models of the Pentium 4 processor, this flag (bit 6) is reserved. See Section 11.6.3, “Checking for the DAZ\nFlag in the MXCSR Register,” for instructions for detecting the availability of this feature.\nAttempting to set bit 6 of the MXCSR register on processors that do not support the DAZ flag will cause a general-\nprotection exception (#GP). See Section 11.6.6, “Guidelines for Writing to the MXCSR Register,” for instructions for\npreventing such general-protection exceptions by using the MXCSR_MASK value returned by the FXSAVE instruc-\ntion.\n\n\n\n10.2.4      Compatibility of Intel® SSE with Intel® SSE2 and SSE3, MMX, and the x87 FPU\nThe state (XMM registers and MXCSR register) introduced into the IA-32 execution environment with Intel SSE is\nshared with Intel SSE2 and SSE3. Intel SSE, SSE2, and SSE3 instructions are fully compatible; they can be\nexecuted together in the same instruction stream with no need to save state when switching between instruction\nsets.\nXMM registers are independent of the x87 FPU and MMX registers, so Intel SSE, SSE2, and SSE3 operations\nperformed on the XMM registers can be performed in parallel with operations on the x87 FPU and MMX registers;\nsee Section 11.6.7, “Interaction of Intel® SSE and SSE2 Instructions with x87 FPU and MMX Instructions.”\nThe FXSAVE and FXRSTOR instructions save and restore the SSE/SSE2/SSE3 states along with the x87 FPU and\nMMX state.\n\n\n\n10.3        INTEL® SSE DATA TYPES\nIntel SSE introduced one data type, the 128-bit packed single precision floating-point data type, to the IA-32 archi-\ntecture (see Figure 10-4). This data type consists of four IEEE 32-bit single precision floating-point values packed\n\n\n\n\n                                                                                                           Vol. 1 10-5"
      },
      {
        "page": 258,
        "id": "physical-page-258",
        "text": "PROGRAMMING WITH INTEL® STREAMING SIMD EXTENSIONS (INTEL® SSE)\n\n\ninto a double quadword. See Figure 4-3 for the layout of a single precision floating-point value; refer to Section\n4.2.2, “Floating-Point Data Types,” for a detailed description of the single precision floating-point format.\n\n\n\n                                                                              Contains 4 Single Precision\n                                                                              Floating-Point Values\n                  127          96 95         64 63         32 31          0\n\n                        Figure 10-4. 128-Bit Packed Single Precision Floating-Point Data Type\n\nThis 128-bit packed single precision floating-point data type is operated on in the XMM registers or in memory.\nConversion instructions are provided to convert two packed single precision floating-point values into two packed\ndoubleword integers or a scalar single precision floating-point value into a doubleword integer (see Figure 11-8).\nIntel SSE provides conversion instructions between XMM registers and MMX registers, and between XMM registers\nand general-purpose bit registers. See Figure 11-8.\nThe address of a 128-bit packed memory operand must be aligned on a 16-byte boundary, except in the following\ncases:\n•   The MOVUPS instruction supports unaligned accesses.\n•   Scalar instructions that use a 4-byte memory operand that is not subject to alignment requirements.\nFigure 4-2 shows the byte order of 128-bit (double quadword) data types in memory.\n\n\n\n10.4          INTEL® SSE INSTRUCTION SET\nIntel SSE instructions are divided into four functional groups:\n•   Packed and scalar single precision floating-point instructions.\n•   64-bit SIMD integer instructions.\n•   State management instructions.\n•   Cacheability control, prefetch, and memory ordering instructions.\nThe following sections give an overview of each of the instructions in these groups.\n\n\n\n10.4.1        Intel® SSE Packed and Scalar Floating-Point Instructions\nThe packed and scalar single precision floating-point instructions are divided into the following subgroups:\n•   Data movement instructions.\n•   Arithmetic instructions.\n•   Logical instructions.\n•   Comparison instructions.\n•   Shuffle instructions.\n•   Conversion instructions.\nThe packed single precision floating-point instructions perform SIMD operations on packed single precision\nfloating-point operands (see Figure 10-5). Each source operand contains four single precision floating-point values,\nand the destination operand contains the results of the operation (OP) performed in parallel on the corresponding\nvalues (X0 and Y0, X1 and Y1, X2 and Y2, and X3 and Y3) in each operand.\n\n\n\n\n10-6 Vol. 1"
      },
      {
        "page": 259,
        "id": "physical-page-259",
        "text": "PROGRAMMING WITH INTEL® STREAMING SIMD EXTENSIONS (INTEL® SSE)\n\n\n\n\n                                X3             X2                  X1               X0\n\n\n\n\n                                     Y3          Y2                  Y1             Y0\n\n\n                                 OP             OP                  OP             OP\n\n\n\n                              X3 OP Y3       X2 OP Y2            X1 OP Y1         X0 OP Y0\n\n                          Figure 10-5. Packed Single Precision Floating-Point Operation\n\nThe scalar single precision floating-point instructions operate on the low (least significant) doublewords of the two\nsource operands (X0 and Y0); see Figure 10-6. The three most significant doublewords (X1, X2, and X3) of the first\nsource operand are passed through to the destination. The scalar operations are similar to the floating-point oper-\nations performed in the x87 FPU data registers with the precision control field in the x87 FPU control word set for\nsingle precision (24-bit significand), except that x87 stack operations use a 15-bit exponent range for the result,\nwhile SSE operations use an 8-bit exponent range.\n\n\n\n                                 X3             X2                  X1             X0\n\n\n\n\n                                     Y3             Y2                  Y1          Y0\n\n\n                                                                                   OP\n\n\n\n                                 X3             X2                  X1          X0 OP Y0\n\n\n                           Figure 10-6. Scalar Single Precision Floating-Point Operation\n\n\n10.4.1.1    Intel® SSE Data Movement Instructions\nIntel SSE data movement instructions move single precision floating-point data between XMM registers and\nbetween an XMM register and memory.\nThe MOVAPS (move aligned packed single precision floating-point values) instruction transfers a double quadword\noperand containing four packed single precision floating-point values from memory to an XMM register and vice\nversa, or between XMM registers. The memory address must be aligned to a 16-byte boundary; otherwise, a\ngeneral-protection exception (#GP) is generated.\nThe MOVUPS (move unaligned packed single precision, floating-point) instruction performs the same operations as\nthe MOVAPS instruction, except that 16-byte alignment of a memory address is not required.\nThe MOVSS (move scalar single precision floating-point) instruction transfers a 32-bit single precision floating-\npoint operand from memory to the low doubleword of an XMM register and vice versa, or between XMM registers.\nThe MOVLPS (move low packed single precision floating-point) instruction moves two packed single precision\nfloating-point values from memory to the low quadword of an XMM register and vice versa. The high quadword of\nthe register is left unchanged.\n\n\n\n\n                                                                                                             Vol. 1 10-7"
      },
      {
        "page": 260,
        "id": "physical-page-260",
        "text": "PROGRAMMING WITH INTEL® STREAMING SIMD EXTENSIONS (INTEL® SSE)\n\n\nThe MOVHPS (move high packed single precision floating-point) instruction moves two packed single precision\nfloating-point values from memory to the high quadword of an XMM register and vice versa. The low quadword of\nthe register is left unchanged.\nThe MOVLHPS (move packed single precision floating-point low to high) instruction moves two packed single preci-\nsion floating-point values from the low quadword of the source XMM register into the high quadword of the desti-\nnation XMM register. The low quadword of the destination register is left unchanged.\nThe MOVHLPS (move packed single precision floating-point high to low) instruction moves two packed single preci-\nsion floating-point values from the high quadword of the source XMM register into the low quadword of the desti-\nnation XMM register. The high quadword of the destination register is left unchanged.\nThe MOVMSKPS (move packed single precision floating-point mask) instruction transfers the most significant bit of\neach of the four packed single precision floating-point numbers in an XMM register to a general-purpose register.\nThis 4-bit value can then be used as a condition to perform branching.\n\n\n10.4.1.2      Intel® SSE Arithmetic Instructions\nIntel SSE arithmetic instructions perform addition, subtraction, multiply, divide, reciprocal, square root, reciprocal\nof square root, and maximum/minimum operations on packed and scalar single precision floating-point values.\nThe ADDPS (add packed single precision floating-point values) and SUBPS (subtract packed single precision\nfloating-point values) instructions add and subtract, respectively, two packed single precision floating-point oper-\nands.\nThe ADDSS (add scalar single precision floating-point values) and SUBSS (subtract scalar single precision floating-\npoint values) instructions add and subtract, respectively, the low single precision floating-point values of two oper-\nands and store the result in the low doubleword of the destination operand.\nThe MULPS (multiply packed single precision floating-point values) instruction multiplies two packed single preci-\nsion floating-point operands.\nThe MULSS (multiply scalar single precision floating-point values) instruction multiplies the low single precision\nfloating-point values of two operands and stores the result in the low doubleword of the destination operand.\nThe DIVPS (divide packed, single precision floating-point values) instruction divides two packed single precision\nfloating-point operands.\nThe DIVSS (divide scalar single precision floating-point values) instruction divides the low single precision floating-\npoint values of two operands and stores the result in the low doubleword of the destination operand.\nThe RCPPS (compute reciprocals of packed single precision floating-point values) instruction computes the approx-\nimate reciprocals of values in a packed single precision floating-point operand.\nThe RCPSS (compute reciprocal of scalar single precision floating-point values) instruction computes the approxi-\nmate reciprocal of the low single precision floating-point value in the source operand and stores the result in the\nlow doubleword of the destination operand.\nThe SQRTPS (compute square roots of packed single precision floating-point values) instruction computes the\nsquare roots of the values in a packed single precision floating-point operand.\nThe SQRTSS (compute square root of scalar single precision floating-point values) instruction computes the square\nroot of the low single precision floating-point value in the source operand and stores the result in the low double-\nword of the destination operand.\nThe RSQRTPS (compute reciprocals of square roots of packed single precision floating-point values) instruction\ncomputes the approximate reciprocals of the square roots of the values in a packed single precision floating-point\noperand.\nThe RSQRTSS (reciprocal of square root of scalar single precision floating-point value) instruction computes the\napproximate reciprocal of the square root of the low single precision floating-point value in the source operand and\nstores the result in the low doubleword of the destination operand.\nThe MAXPS (return maximum of packed single precision floating-point values) instruction compares the corre-\nsponding values from two packed single precision floating-point operands and returns the numerically greater\nvalue from each comparison to the destination operand.\n\n\n\n10-8 Vol. 1"
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        "page": 323,
        "id": "physical-page-323",
        "text": "MANAGING STATE USING THE XSAVE FEATURE SET\n\n\nSome XSAVE-supported features can be used only if XCR0 has been configured so that the features’ state compo-\nnents can be managed by the XSAVE feature set. (This applies only to features with user state components.) Such\nstate components and features are XSAVE-enabled. In general, the processor will not modify (or allow modifica-\ntion of) the registers of a state component of an XSAVE-enabled feature if the bit corresponding to that state\ncomponent is clear in XCR0. (If software clears such a bit in XCR0, the processor preserves the corresponding state\ncomponent.) If an XSAVE-enabled feature has not been fully enabled in XCR0, execution of any instruction defined\nfor that feature causes an invalid-opcode exception (#UD).\nAs will be explained in Section 13.3, the XSAVE feature set is enabled only if CR4.OSXSAVE[bit 18] = 1. If\nCR4.OSXSAVE = 0, the processor treats XSAVE-enabled state features and their state components as if all bits in\nXCR0 were clear; the state components cannot be modified and the features’ instructions cannot be executed.\nThe state components for x87 state, for SSE state, for PT state, for PKRU state, for PASID state, for CET state, for\nHDC state, for UINTR state, for LBR state, and for HWP state are XSAVE-managed but the corresponding features\nare not XSAVE-enabled. Processors allow modification of this state, as well as execution of x87 FPU instructions\nand SSE instructions and use of Intel Processor Trace, protection keys, the ENQCMD instruction and the\nIA32_PASID MSR, CET, hardware duty cycling, user interrupts, LBRs, and hardware P-states, regardless of the\nvalue of CR4.OSXSAVE and XCR0.\n\n\n\n13.2        ENUMERATION OF CPU SUPPORT FOR XSAVE INSTRUCTIONS AND XSAVE-\n            SUPPORTED FEATURES\nA processor enumerates support for the XSAVE feature set and for features supported by that feature set using the\nCPUID instruction. The following items provide specific details:\n•   CPUID.01H:ECX.XSAVE[26] enumerates general support for the XSAVE feature set:\n    — If this bit is 0, the processor does not support any of the following instructions: XGETBV, XRSTOR,\n      XRSTORS, XSAVE, XSAVEC, XSAVEOPT, XSAVES, and XSETBV; the processor provides no further\n      enumeration through CPUID.0DH (see below).\n    — If this bit is 1, the processor supports the following instructions: XGETBV, XRSTOR, XSAVE, and XSETBV.1\n      Further enumeration is provided through CPUID.0DH.\n    CR4.OSXSAVE can be set to 1 if and only if CPUID.01H:ECX.XSAVE[26] is enumerated as 1.\n•   CPUID.0DH enumerates details of CPU support through a set of sub-leaves. Software selects a specific sub-leaf\n    by the value placed in the ECX register. The following items provide specific details:\n    — CPUID.0DH.00H.\n        •   EDX:EAX is a bitmap of all the user state components that can be managed using the XSAVE feature\n            set. A bit can be set in XCR0 if and only if the corresponding bit is set in this bitmap. Every processor\n            that supports the XSAVE feature set will set EAX[0] (x87 state) and EAX[1] (SSE state).\n            If EAX[i] = 1 (for 1 < i < 32) or EDX[i–32] = 1 (for 32 ≤ i < 63), sub-leaf i enumerates details for state\n            component i (see below).\n        •   ECX enumerates the size (in bytes) required by the XSAVE instruction for an XSAVE area containing all\n            the user state components supported by this processor.\n        •   EBX enumerates the size (in bytes) required by the XSAVE instruction for an XSAVE area containing all\n            the user state components corresponding to bits currently set in XCR0.\n    — CPUID.0DH.01H.\n        •   EAX[0] enumerates support for the XSAVEOPT instruction. The instruction is supported if and only if\n            this bit is 1. If EAX[0] = 0, execution of XSAVEOPT causes an invalid-opcode exception (#UD).\n        •   EAX[1] enumerates support for compaction extensions to the XSAVE feature set. The following are\n            supported if this bit is 1:\n\n\n1. If CPUID.01H:ECX.XSAVE[26] = 1, XGETBV and XSETBV may be executed with ECX = 0 (to read and write XCR0). Any support for\n   execution of these instructions with other values of ECX is enumerated separately.\n\n\n                                                                                                                  Vol. 1 13-3"
      },
      {
        "page": 360,
        "id": "physical-page-360",
        "text": "PROGRAMMING WITH INTEL® AVX, FMA, AND INTEL® AVX2\n\n\n          Table 14-5. Promotion of Legacy SIMD ISA to 128-Bit Arithmetic Intel® AVX Instructions (Contd.)\n      VEX.256           VEX.128\n                                                          Instruction                      Reason Not Promoted\n      Encoding          Encoding\n no               yes              PMADDWD, PMADDUBSW                                 VI\n no               yes              PAVGB, PAVGW, PMULUDQ                              VI\n no               yes              PCMPEQB, PCMPEQW, PCMPEQD                          VI\n no               yes              PMULLW, PMULHUW, PMULHW                            VI\n no               yes              PSUBSW, PADDSW, PSADBW                             VI\n no               yes              PADDUSB, PADDUSW, PADDSB                           VI\n no               yes              PSUBUSB, PSUBUSW, PSUBSB                           VI\n no               yes              PMINUB, PMINSW                                     VI\n no               yes              PMAXUB, PMAXSW                                     VI\n no               yes              PADDB, PADDW, PADDD, PADDQ                         VI\n no               yes              PSUBB, PSUBW, PSUBD, PSUBQ                         VI\n no               yes              PSLLW, PSLLD, PSLLQ, PSRAW                         VI\n no               yes              PSRLW, PSRLD, PSRLQ, PSRAD                         VI\n                                                CPUID.01H:ECX.SSSE3[9]\n no               yes              PHSUBW, PHSUBD, PHSUBSW                            VI\n no               yes              PHADDW, PHADDD, PHADDSW                            VI\n no               yes              PMULHRSW                                           VI\n no               yes              PSIGNB, PSIGNW, PSIGND                             VI\n no               yes              PABSB, PABSW, PABSD                                VI\n                                               CPUID.01H:ECX.SSE4_1[19]\n no               yes              DPPD\n no               yes              PHMINPOSUW, MPSADBW                                VI\n no               yes              PMAXSB, PMAXSD, PMAXUD                             VI\n no               yes              PMINSB, PMINSD, PMINUD                             VI\n no               yes              PMAXUW, PMINUW                                     VI\n no               yes              PMOVSXxx, PMOVZXxx                                 VI\n no               yes              PMULDQ, PMULLD                                     VI\n no               yes              ROUNDSD, ROUNDSS                                   Scalar\n                                               CPUID.01H:ECX.POPCNT[23]\n no               yes              POPCNT                                             Integer\n                                               CPUID.01H:ECX.SSE4_2[20]\n no               yes              PCMPGTQ                                            VI\n no               no               CRC32                                              Integer\n no               yes              PCMPESTRI, PCMPESTRM                               VI\n no               yes              PCMPISTRI, PCMPISTRM                               VI\n                                              CPUID.01H:ECX.PCLMULQDQ[1]\n no               yes              PCLMULQDQ                                          VI\n                                                CPUID.01H:ECX.AESNI[25]\n\n\n14-12 Vol. 1"
      },
      {
        "page": 361,
        "id": "physical-page-361",
        "text": "PROGRAMMING WITH INTEL® AVX, FMA, AND INTEL® AVX2\n\n\n          Table 14-5. Promotion of Legacy SIMD ISA to 128-Bit Arithmetic Intel® AVX Instructions (Contd.)\n      VEX.256            VEX.128\n                                                            Instruction                                Reason Not Promoted\n      Encoding           Encoding\n\n no                yes               AESDEC, AESDECLAST                                           VI\n no                yes               AESENC, AESENCLAST                                           VI\n no                yes               AESIMX, AESKEYGENASSIST                                      VI\n\nDescription of Column “Reason not promoted”:\n•     MMX: Instructions referencing MMX registers do not support VEX.\n•     Scalar: Scalar instructions are not promoted to 256-bit.\n•     Integer: Integer instructions are not promoted.\n•     VI: “Vector Integer” instructions are not promoted to 256-bit.\n\n\n\n14.2.4        Non-Arithmetic Primitives for 128-Bit Vector and Scalar Processing\nIntel AVX provides a full complement of data processing instructions that employ VEX-prefix encoding. These VEX-\nencoded instructions generally provide the same functionality over instructions operating on XMM register that are\nencoded using SIMD prefixes.\nA subset of new functionalities listed in Table 14-4 is also extended via VEX.128 encoding. These enhancements in\nAVX on 128-bit data processing primitives include 11 new instructions (see Table 14-6) with the following capabil-\nities:\n•     Non-unit-strided fetching of SIMD data. AVX provides several flexible SIMD floating-point data fetching\n      primitives:\n      — broadcast of single data element into a 128-bit destination,\n      — masked move primitives to load or store SIMD data elements conditionally,\n•     Intra-register manipulation of SIMD data elements. AVX provides several flexible SIMD floating-point data\n      manipulation primitives:\n      — permute primitives to facilitate efficient manipulation of floating-point data elements in 128-bit SIMD\n        registers\n•     Branch handling. AVX provides several primitives to enable handling of branches in SIMD programming:\n      — new variable blend instructions supports four-operand syntax with non-destructive source syntax.\n        Branching conditions dependent on floating-point data or integer data can benefit from Intel AVX. This is\n        more flexible than non-VEX encoded instruction syntax that uses the XMM0 register as implied mask for\n        blend selection. While variable blend with implied XMM0 syntax is supported in SSE4 using SIMD prefix\n        encoding, VEX-encoded 128-bit variable blend instructions only support the more flexible four-operand\n        syntax.\n      — Packed TEST instructions for floating-point data.\n\n\n                                Table 14-6. 128-Bit Intel® AVX Instruction Enhancement\nInstruction                              Description\nVBROADCASTSS xmm1, m32                   Broadcast single precision floating-point element in mem to four locations in xmm1.\nVMASKMOVPS xmm1, xmm2, m128              Load packed single precision values from mem using mask in xmm2 and store in xmm1.\nVMASKMOVPD xmm1, xmm2, m128              Load packed double precision values from mem using mask in xmm2 and store in xmm1.\nVMASKMOVPS m128, xmm1, xmm2              Store packed single precision values from xmm2 using mask in xmm1.\nVMASKMOVPD m128, xmm1, xmm2              Store packed double precision values from xmm2 using mask in xmm1.\n\n\n\n\n                                                                                                                      Vol. 1 14-13"
      },
      {
        "page": 362,
        "id": "physical-page-362",
        "text": "PROGRAMMING WITH INTEL® AVX, FMA, AND INTEL® AVX2\n\n\n                             Table 14-6. 128-Bit Intel® AVX Instruction Enhancement (Contd.)\n Instruction                              Description\n VPERMILPD xmm1, xmm2, xmm3/m128          Permute double precision floating-point values in xmm2 using controls from xmm3/mem\n                                          and store result in xmm1.\n VPERMILPD xmm1, xmm2/m128, imm8          Permute double precision floating-point values in xmm2/mem using controls from imm8\n                                          and store result in xmm1.\n VPERMILPS xmm1, xmm2, xmm3/m128          Permute single precision floating-point values in xmm2 using controls from xmm3/mem\n                                          and store result in xmm1.\n VPERMILPS xmm1, xmm2/m128, imm8          Permute single precision floating-point values in xmm2/mem using controls from imm8\n                                          and store result in xmm1.\n VTESTPS xmm1, xmm2/m128                  Set ZF if xmm2/mem AND xmm1 result is all 0s in packed single precision sign bits. Set CF\n                                          if xmm2/mem AND NOT xmm1 result is all 0s in packed single precision sign bits.\n VTESTPD xmm1, xmm2/m128                  Set ZF if xmm2/mem AND xmm1 result is all 0s in packed single precision sign bits. Set CF\n                                          if xmm2/mem AND NOT xmm1 result is all 0s in packed double precision sign bits.\n\n\n\nThe 128-bit data processing instructions in AVX cover floating-point and integer data movement primitives. Legacy\nSIMD non-arithmetic ISA promoted to VEX-256 encoding also support VEX-128 encoding (see Table 14-3). Table\n14-7 lists the state of promotion of the remaining legacy SIMD non-arithmetic ISA to VEX-128 encoding.\n\n\n               Table 14-7. Promotion of Legacy SIMD ISA to 128-Bit Non-Arithmetic Intel® AVX instruction\n      VEX.256             VEX.128\n                                                             Instruction                                 Reason Not Promoted\n      Encoding            Encoding\n\n no                 no                MOVQ2DQ, MOVDQ2Q                                              MMX\n no                 yes               LDMXCSR, STMXCSR\n no                 yes               MOVSS, MOVSD, CMPSS, CMPSD                                    Scalar\n no                 yes               MOVHPS, MOVHPD                                                Note 1\n no                 yes               MOVLPS, MOVLPD                                                Note 1\n no                 yes               MOVLHPS, MOVHLPS                                              Redundant with VPERMILPS\n no                 yes               MOVQ, MOVD                                                    Scalar\n no                 yes               PACKUSWB, PACKSSDW, PACKSSWB                                  VI\n no                 yes               PUNPCKHBW, PUNPCKHWD                                          VI\n no                 yes               PUNPCKLBW, PUNPCKLWD                                          VI\n no                 yes               PUNPCKHDQ, PUNPCKLDQ                                          VI\n no                 yes               PUNPCKLQDQ, PUNPCKHQDQ                                        VI\n no                 yes               PSHUFHW, PSHUFLW, PSHUFD                                      VI\n no                 yes               PMOVMSKB, MASKMOVDQU                                          VI\n no                 yes               PAND, PANDN, POR, PXOR                                        VI\n no                 yes               PINSRW, PEXTRW,                                               VI\n                                                    CPUID.01H:ECX.SSSE3[9]\n no                 yes               PALIGNR, PSHUFB                                               VI\n                                                   CPUID.01H:ECX.SSE4_1[19]\n no                 yes               EXTRACTPS, INSERTPS                                           Note 3\n no                 yes               PACKUSDW, PCMPEQQ                                             VI\n\n\n14-14 Vol. 1"
      },
      {
        "page": 363,
        "id": "physical-page-363",
        "text": "PROGRAMMING WITH INTEL® AVX, FMA, AND INTEL® AVX2\n\n\n       Table 14-7. Promotion of Legacy SIMD ISA to 128-Bit Non-Arithmetic Intel® AVX instruction (Contd.)\n     VEX.256            VEX.128\n                                                                Instruction                              Reason Not Promoted\n     Encoding           Encoding\n\nno                yes                  PBLENDVB, PBLENDW                                            VI\nno                yes                  PEXTRW, PEXTRB, PEXTRD, PEXTRQ                               VI\nno                yes                  PINSRB, PINSRD, PINSRQ                                       VI\n\nDescription of column “Reason not promoted”:\n•    MMX: Instructions referencing MMX registers do not support VEX.\n•    Scalar: Scalar instructions are not promoted to 256-bit.\n•    VI: “Vector Integer” instructions are not promoted to 256-bit.\n•    Note 1: MOVLPD/PS and MOVHPD/PS are not promoted to 256-bit. The equivalent functionality are provided\n     by VINSERTF128 and VEXTRACTF128 instructions as the existing instructions have no natural 256b extension\n•    Note 3: It is expected that using 128-bit INSERTPS followed by a VINSERTF128 would be better than\n     promoting INSERTPS to 256-bit (for example).\n\n\n\n14.3         DETECTION OF INTEL® AVX INSTRUCTIONS\nIntel AVX instructions operate on the 256-bit YMM register state. Application detection of new instruction exten-\nsions operating on the YMM state follows the general procedural flow in Figure 14-2.\nPrior to using Intel AVX, the application must identify that the operating system supports the XGETBV instruction,\nthe YMM register state, in addition to processor’s support for YMM state management using XSAVE/XRSTOR and\nAVX instructions. The following simplified sequence accomplishes both and is strongly recommended.\n1) Detect CPUID.01H:ECX.OSXSAVE[27] = 1 (XGETBV enabled for application use1).\n2) Issue XGETBV and verify that XCR0[2:1] = ‘11b’ (XMM state and YMM state are enabled by OS).\n3) detect CPUID.01H:ECX.AVX[28] = 1 (AVX instructions supported).\n(Step 3 can be done in any order relative to 1 and 2.)\n\n\n\n\n                               Check feature flag\n                               CPUID.1H:ECX.OSXSAVE = 1?\n\n\n                                      Yes   OS provides processor\n                                              extended state management\n                                                Implied HW support for\n                                                XSAVE, XRSTOR, XGETBV, XCR0\n\n\n\n                                   Check enabled state in                 Check feature flag\n                                   XCR0 via XGETBV           State          for Instruction set    ok to use\n                                                             enabled                               Instructions\n\n\n                     Figure 14-2. General Procedural Flow of Application Detection of Intel® AVX\n\n\n1. If CPUID.01H:ECX.OSXSAVE reports 1, it also indirectly implies the processor supports XSAVE, XRSTOR, XGETBV, processor\n   extended state bit vector XCR0. Thus an application may streamline the checking of CPUID feature flags for XSAVE and OSXSAVE.\n   XSETBV is a privileged instruction.\n\n\n                                                                                                                      Vol. 1 14-15"
      },
      {
        "page": 364,
        "id": "physical-page-364",
        "text": "PROGRAMMING WITH INTEL® AVX, FMA, AND INTEL® AVX2\n\n\nThe following pseudocode illustrates this recommended application Intel AVX detection process:\n\nExample 14-1. Detection of Intel® AVX Instruction\n\nINT supports_AVX()\n{ mov        eax, 1\n   cpuid\n   and       ecx, 018000000H\n   cmp       ecx, 018000000H; check both OSXSAVE and AVX feature flags\n    jne      not_supported\n   ; processor supports AVX instructions and XGETBV is enabled by OS\n   mov       ecx, 0; specify 0 for XCR0 register\n   XGETBV              ; result in EDX:EAX\n   and       eax, 06H\n   cmp       eax, 06H; check OS has enabled both XMM and YMM state support\n   jne       not_supported\n   mov       eax, 1\n   jmp       done\nNOT_SUPPORTED:\n   mov       eax, 0\n   done:\n}\n\n\n                                                          NOTE\n         It is unwise for an application to rely exclusively on CPUID.01H:ECX.AVX[28] or at all on\n         CPUID.01H:ECX.XSAVE[26]: These indicate hardware support but not operating system support. If\n         YMM state management is not enabled by an operating systems, Intel AVX instructions will #UD\n         regardless of CPUID.01H:ECX.AVX[28]. “CPUID.01H:ECX.XSAVE[26] = 1” does not guarantee the\n         OS actually uses the XSAVE process for state management.\n\n\nThese steps above also apply to enhanced 128-bit SIMD floating-pointing instructions in Intel AVX (using VEX\nprefix-encoding) that operate on the YMM states.\n\n\n\n\n14-16 Vol. 1"
      },
      {
        "page": 365,
        "id": "physical-page-365",
        "text": "PROGRAMMING WITH INTEL® AVX, FMA, AND INTEL® AVX2\n\n\n\n14.3.1      Detection of VEX-Encoded AES and VPCLMULQDQ\nThe VAESDEC/VAESDECLAST/VAESENC/VAESENCLAST/VAESIMC/VAESKEYGENASSIST instructions operate on\nYMM states. The detection sequence must combine checking for CPUID.01H:ECX.AES[25] = 1 and the sequence\nfor detection application support for Intel AVX.\n\nExample 14-2. Detection of VEX-Encoded Intel® AES-NI Instructions\n\nINT supports_VAESNI()\n{ mov        eax, 1\n   cpuid\n   and       ecx, 01A000000H\n   cmp       ecx, 01A000000H; check OSXSAVE AVX and AESNI feature flags\n    jne      not_supported\n   ; processor supports AVX and VEX-encoded AESNI and XGETBV is enabled by OS\n   mov       ecx, 0; specify 0 for XCR0 register\n   XGETBV              ; result in EDX:EAX\n   and       eax, 06H\n   cmp       eax, 06H; check OS has enabled both XMM and YMM state support\n   jne       not_supported\n   mov       eax, 1\n   jmp       done\nNOT_SUPPORTED:\n   mov       eax, 0\ndone:\n\n\nSimilarly, the detection sequence for VPCLMULQDQ must combine checking for CPUID.01H:ECX.PCLMULQDQ[1] =\n1 and the sequence for detection application support for Intel AVX.\nThis is shown in the pseudocode provided in Example 14-3.\n\nExample 14-3. Detection of VEX-Encoded Intel® AES-NI Instructions\n\nINT supports_VPCLMULQDQ)\n{ mov        eax, 1\n   cpuid\n   and       ecx, 018000002H\n   cmp       ecx, 018000002H; check OSXSAVE AVX and PCLMULQDQ feature flags\n    jne      not_supported\n   ; processor supports AVX and VEX-encoded PCLMULQDQ and XGETBV is enabled by OS\n   mov       ecx, 0; specify 0 for XCR0 register\n   XGETBV              ; result in EDX:EAX\n   and       eax, 06H\n   cmp       eax, 06H; check OS has enabled both XMM and YMM state support\n   jne       not_supported\n\n\n   mov   eax, 1\n   jmp   done\nNOT_SUPPORTED:\n   mov   eax, 0\ndone:\n\n\n\n\n                                                                                                           Vol. 1 14-17"
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      {
        "id": "leaf-254",
        "level": 0,
        "summary": "Intel® Streaming SIMD Extensions (Intel® SSE) is fully compatible with IA-32 processor software, allowing existing software to run unmodified on SSE-incorporating processors. CPUID enhancements enable SSE detection, and SSE is accessible in all IA-32 execution modes (protected, real address, virtual-8086). The chapter describes the SSE programming environment, including XMM registers, packed single precision floating-point data type, and SSE instructions. Additional details are in sections 11.5 (exceptions), 11.6 (application writing), the Intel® 64 and IA-32 Architectures Software Developer’s Manual Volumes 2A-2D (instruction descriptions), and Volume 3A Chapter 16 (OS integration). The SSE execution environment includes eight 128-bit XMM registers (XMM0-XMM7) for packed/scalar single precision floating-point operations; a 32-bit MXCSR register for SIMD floating-point status/control; eight 64-bit MMX registers (MM0-MM7) for packed integer data and XMM operand interaction; and eight 32-bit general-purpose registers for memory addressing (MMX/XMM registers cannot address memory).",
        "key_terms": [
          "Intel® Streaming SIMD Extensions (Intel® SSE)",
          "IA-32 processors",
          "CPUID",
          "execution modes",
          "protected mode",
          "real address mode",
          "virtual-8086 mode",
          "programming environment",
          "XMM registers",
          "packed single precision floating-point data type",
          "Intel SSE instructions",
          "MXCSR register",
          "MMX registers",
          "general-purpose registers",
          "SIMD floating-point operations"
        ],
        "source_pages": [
          254
        ],
        "children": [],
        "text_preview": "PROGRAMMING WITH INTEL® STREAMING SIMD EXTENSIONS (INTEL® SSE)\n\n\nIntel SSE is fully compatible with all software written for IA-32 processors. All existing software continues to run\ncorrectly, without modification, on processors that incorporate Intel SSE. Enhancements to CPUID permit detection\nof Intel SSE. Intel SSE is accessible from all IA-32 execution modes: protected mode, real address mode, and\nvirtual-8086 mode.\nThe following sections of this chapter describe the programming environment for Intel SSE, including: XMM regis-\nters, the packed single precision floating-point data type, and Intel SSE instructions. For additional information,\nsee:\n•   Section 11.6, “Writing Applications with Intel® SSE and SSE2.”\n•   Section 11.5, “Intel® SSE, SSE2, and SSE3 Exceptions,” describes the exceptions that can be generated with\n    Intel SSE/SSE2/SSE3 instructions.\n•   The Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volumes 2A, 2B, 2C, & 2D, provides a\n    detailed description of these instructions.\n•   Chapter 16, “System Programming for Instruction Set Extensions and Processor Extended States,” in the Intel®\n    64 and IA-32 Architectures Software Developer’s Manua"
      },
      {
        "id": "leaf-255",
        "level": 0,
        "summary": "This section covers programming with Intel® Streaming SIMD Extensions (Intel® SSE), including its behavior in 64-bit and compatibility modes, XMM registers, and the MXCSR control and status register. In compatibility mode, SSE functions like in protected mode; 64-bit mode adds eight additional XMM registers (XMM8-XMM15) accessible via REX prefixes, with memory operands using ModR/M, SIB encoding. Some SSE instructions use general-purpose registers, with REX.W prefix for 64-bit general-purpose registers (ignored if meaningless). Intel SSE introduced eight 128-bit XMM registers (XMM0-XMM7), independent of other registers, used for packed single precision floating-point operands (SSE2 expands to handle packed/scalar double precision floating-point and packed integer operands). XMM registers cannot address memory (done via general-purpose registers) but can load/store data in 32, 64, 128-bit increments; 128-bit store uses 16 consecutive bytes with low-order byte first. The 32-bit MXCSR register contains control/status info for SSE/SSE2/SSE3 SIMD floating-point operations, including exception flag/mask bits and rounding control field.",
        "key_terms": [
          "Intel® Streaming SIMD Extensions (Intel® SSE)",
          "64-bit mode",
          "compatibility mode",
          "XMM registers",
          "XMM0-XMM7",
          "XMM8-XMM15",
          "REX prefixes",
          "ModR/M, SIB encoding",
          "general-purpose registers",
          "128-bit",
          "packed single precision floating-point operands",
          "SSE2",
          "MXCSR control and status register",
          "SIMD floating-point exceptions",
          "rounding control field"
        ],
        "source_pages": [
          255
        ],
        "children": [],
        "text_preview": "PROGRAMMING WITH INTEL® STREAMING SIMD EXTENSIONS (INTEL® SSE)\n\n\n    address memory). The general-purpose registers are also used to hold operands for some SSE instructions and\n    are referenced as EAX, EBX, ECX, EDX, EBP, ESI, EDI, and ESP.\n•   EFLAGS register — This 32-bit register (see Figure 3-7) is used to record result of some compare operations.\n\n\n\n10.2.1      Intel® SSE in 64-Bit Mode and Compatibility Mode\nIn compatibility mode, Intel SSE functions like it does in protected mode. In 64-bit mode, eight additional XMM\nregisters are accessible. Registers XMM8-XMM15 are accessed by using REX prefixes. Memory operands are spec-\nified using the ModR/M, SIB encoding described in Section 3.7.5.\nSome Intel SSE instructions may be used to operate on general-purpose registers. Use the REX.W prefix to access\n64-bit general-purpose registers. Note that if a REX prefix is used when it has no meaning, the prefix is ignored.\n\n\n\n10.2.2      XMM Registers\nEight 128-bit XMM data registers were introduced into the IA-32 architecture with Intel SSE (see Figure 10-2).\nThese registers can be accessed directly using the names XMM0 to XMM7; and they can be accessed independently\nfrom the x87 FPU "
      },
      {
        "id": "leaf-256",
        "level": 0,
        "summary": "This section covers programming with Intel® Streaming SIMD Extensions (Intel® SSE), focusing on the MXCSR control/status register. It includes flags such as Flush-to-zero (controlling underflow conditions) and Denormals-are-zeros (handling denormal source operands). The MXCSR register can be loaded from memory using LDMXCSR and FXRSTOR, and stored to memory with STMXCSR and FXSAVE. Bits 16-31 are reserved; writing non-zero values here causes a general-protection exception (#GP). SIMD floating-point mask and flag bits: bits 0-5 are sticky exception flags (cleared by LDMXCSR/FXRSTOR), bits 7-12 are exception mask bits (set on power-up/reset, initially masking all exceptions). Unmasking a mask bit with a set flag does not generate an exception until the next SSE/SSE2/SSE3 instruction detecting the condition. The rounding control field (bits 13-14) controls result rounding of SIMD floating-point instructions. Flush-to-zero (bit 15) enables handling masked underflow conditions.",
        "key_terms": [
          "Intel® Streaming SIMD Extensions (Intel® SSE)",
          "MXCSR control/status register",
          "Flush-to-zero flag",
          "Denormals-are-zeros flag",
          "LDMXCSR",
          "STMXCSR",
          "FXRSTOR",
          "FXSAVE",
          "sticky exception flags",
          "exception mask bits",
          "rounding control field",
          "general-protection exception (#GP)"
        ],
        "source_pages": [
          256
        ],
        "children": [],
        "text_preview": "PROGRAMMING WITH INTEL® STREAMING SIMD EXTENSIONS (INTEL® SSE)\n\n\n•   Flush-to-zero flag that provides a means of controlling underflow conditions on SIMD floating-point operations.\n•   Denormals-are-zeros flag that controls how SIMD floating-point instructions handle denormal source operands.\nThe contents of this register can be loaded from memory with the LDMXCSR and FXRSTOR instructions and stored\nin memory with STMXCSR and FXSAVE.\nBits 16 through 31 of the MXCSR register are reserved and are cleared on a power-up or reset of the processor;\nattempting to write a non-zero value to these bits, using either the FXRSTOR or LDMXCSR instructions, will result\nin a general-protection exception (#GP) being generated.\n\n\n                                    31                                 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0\n\n                                                                          F\n                                                                          T   R   P U O Z D I D P U O Z D I\n                                                 Reserved                                     A\n                                                                          Z   C   M M"
      },
      {
        "id": "leaf-257",
        "level": 0,
        "summary": "The documentation covers programming with Intel® SSE, including flush-to-zero mode (returns zero with sign of true result, sets precision/underflow flags, not IEEE 754 compatible, for performance with common underflows, cleared on power-up/reset). Denormals-Are-Zeros (DAZ) mode (bit 6 of MXCSR; converts denormal operands to zero with original sign before computation, doesn't set DE flag/generate exception, not IEEE 754 compatible, for performance like streaming media, cleared on power-up/reset; introduced in Pentium 4/Xeon with SSE2, compatible with SSE; earlier IA-32/some Pentium 4 have bit 6 reserved; setting unsupported DAZ causes #GP, use FXSAVE's MXCSR_MASK to prevent). SSE compatibility: state (XMM, MXCSR) shared with SSE2/SSE3, instructions compatible (mixable without state saving); XMM registers independent of x87 FPU/MMX (parallel operations possible); FXSAVE/FXRSTOR save/restore SSE/SSE2/SSE3 with x87/MMX state. SSE data types: introduced 128-bit packed single precision floating-point (four 32-bit IEEE values).",
        "key_terms": [
          "Intel® Streaming SIMD Extensions (Intel® SSE)",
          "flush-to-zero mode",
          "underflow exception flags",
          "precision exception flags",
          "IEEE Standard 754",
          "denormals-are-zeros (DAZ) mode",
          "MXCSR register",
          "DE flag (denormal-operand exception flag)",
          "DM bit (denormal-operand exception mask bit)",
          "Pentium 4 processor",
          "Intel Xeon processor",
          "SSE2 extensions",
          "general-protection exception (#GP)",
          "FXSAVE instruction",
          "FXRSTOR instruction",
          "XMM registers",
          "x87 FPU",
          "MMX registers",
          "128-bit packed single precision floating-point data type"
        ],
        "source_pages": [
          257
        ],
        "children": [],
        "text_preview": "PROGRAMMING WITH INTEL® STREAMING SIMD EXTENSIONS (INTEL® SSE)\n\n\n•   Returns a zero result with the sign of the true result.\n•   Sets the precision and underflow exception flags.\nIf the underflow exception is not masked, the flush-to-zero bit is ignored.\nThe flush-to-zero mode is not compatible with IEEE Standard 754. The IEEE-mandated masked response to under-\nflow is to deliver the denormalized result (see Section 4.8.3.2, “Normalized and Denormalized Finite Numbers”).\nThe flush-to-zero mode is provided primarily for performance reasons. At the cost of a slight precision loss, faster\nexecution can be achieved for applications where underflows are common and rounding the underflow result to\nzero can be tolerated.\nThe flush-to-zero bit is cleared upon a power-up or reset of the processor, disabling the flush-to-zero mode.\n\n\n10.2.3.4     Denormals-Are-Zeros\nBit 6 (DAZ) of the MXCSR register enables the denormals-are-zeros mode, which controls the processor’s response\nto a SIMD floating-point denormal operand condition. When the denormals-are-zeros flag is set, the processor\nconverts all denormal source operands to a zero with the sign of the original operand before performing any\nco"
      },
      {
        "id": "leaf-258",
        "level": 0,
        "summary": "This section covers Intel® Streaming SIMD Extensions (Intel® SSE) programming, focusing on the 128-bit packed single precision floating-point data type, which contains four single precision floating-point values and is operated on in XMM registers or memory. Conversion instructions are provided for converting packed/scalar single precision floating-point values to integers, and between XMM, MMX, and general-purpose bit registers. The 128-bit packed memory operand requires 16-byte boundary alignment, except for MOVUPS (supporting unaligned accesses) and scalar 4-byte memory operands (no alignment requirements). Intel SSE instructions are divided into four functional groups: packed/scalar single precision floating-point, 64-bit SIMD integer, state management, and cacheability control/prefetch/memory ordering. Packed and scalar single precision floating-point instructions are further subgrouped into data movement, arithmetic, logical, comparison, shuffle, and conversion instructions; packed instructions perform SIMD operations on four parallel values in operands.",
        "key_terms": [
          "Intel® Streaming SIMD Extensions (Intel® SSE)",
          "128-bit packed single precision floating-point data type",
          "XMM registers",
          "16-byte boundary alignment",
          "MOVUPS instruction",
          "conversion instructions",
          "MMX registers",
          "general-purpose bit registers",
          "Intel SSE instruction set",
          "packed single precision floating-point instructions",
          "scalar single precision floating-point instructions",
          "64-bit SIMD integer instructions",
          "state management instructions",
          "cacheability control instructions",
          "prefetch instructions",
          "memory ordering instructions",
          "data movement instructions",
          "arithmetic instructions",
          "logical instructions",
          "comparison instructions",
          "shuffle instructions"
        ],
        "source_pages": [
          258
        ],
        "children": [],
        "text_preview": "PROGRAMMING WITH INTEL® STREAMING SIMD EXTENSIONS (INTEL® SSE)\n\n\ninto a double quadword. See Figure 4-3 for the layout of a single precision floating-point value; refer to Section\n4.2.2, “Floating-Point Data Types,” for a detailed description of the single precision floating-point format.\n\n\n\n                                                                              Contains 4 Single Precision\n                                                                              Floating-Point Values\n                  127          96 95         64 63         32 31          0\n\n                        Figure 10-4. 128-Bit Packed Single Precision Floating-Point Data Type\n\nThis 128-bit packed single precision floating-point data type is operated on in the XMM registers or in memory.\nConversion instructions are provided to convert two packed single precision floating-point values into two packed\ndoubleword integers or a scalar single precision floating-point value into a doubleword integer (see Figure 11-8).\nIntel SSE provides conversion instructions between XMM registers and MMX registers, and between XMM registers\nand general-purpose bit registers. See Figure 11-8.\nThe address of a 128-bit p"
      },
      {
        "id": "leaf-259",
        "level": 0,
        "summary": "This section covers programming with Intel® Streaming SIMD Extensions (Intel® SSE), focusing on single precision floating-point operations and data movement instructions. Packed single precision floating-point operations (Figure 10-5) operate on all four doublewords (X3-X0 and Y3-Y0) of source operands. Scalar single precision floating-point operations (Figure 10-6) act only on the low doublewords (X0 and Y0), with the three most significant doublewords (X1-X3) of the first source operand passed through to the destination. Scalar operations are similar to x87 FPU operations with single precision (24-bit significand) but differ in exponent range (x87 uses 15-bit, SSE uses 8-bit). Intel SSE data movement instructions (10.4.1.1) include MOVAPS (moves aligned packed single precision between XMM registers/memory; requires 16-byte memory alignment, else #GP exception), MOVUPS (same as MOVAPS without alignment requirement), MOVSS (transfers scalar single precision to/from the low doubleword of an XMM register), and MOVLPS (moves two packed single precision to/from the low quadword of an XMM register, leaving the high quadword unchanged).",
        "key_terms": [
          "Intel® Streaming SIMD Extensions (Intel® SSE)",
          "packed single precision floating-point operation",
          "scalar single precision floating-point operation",
          "XMM registers",
          "MOVAPS",
          "MOVUPS",
          "MOVSS",
          "MOVLPS",
          "16-byte alignment",
          "general-protection exception (#GP)",
          "x87 FPU",
          "24-bit significand",
          "15-bit exponent range",
          "8-bit exponent range"
        ],
        "source_pages": [
          259
        ],
        "children": [],
        "text_preview": "PROGRAMMING WITH INTEL® STREAMING SIMD EXTENSIONS (INTEL® SSE)\n\n\n\n\n                                X3             X2                  X1               X0\n\n\n\n\n                                     Y3          Y2                  Y1             Y0\n\n\n                                 OP             OP                  OP             OP\n\n\n\n                              X3 OP Y3       X2 OP Y2            X1 OP Y1         X0 OP Y0\n\n                          Figure 10-5. Packed Single Precision Floating-Point Operation\n\nThe scalar single precision floating-point instructions operate on the low (least significant) doublewords of the two\nsource operands (X0 and Y0); see Figure 10-6. The three most significant doublewords (X1, X2, and X3) of the first\nsource operand are passed through to the destination. The scalar operations are similar to the floating-point oper-\nations performed in the x87 FPU data registers with the precision control field in the x87 FPU control word set for\nsingle precision (24-bit significand), except that x87 stack operations use a 15-bit exponent range for the result,\nwhile SSE operations use an 8-bit exponent range.\n\n\n\n                                 X3             X"
      },
      {
        "id": "leaf-260",
        "level": 0,
        "summary": "Covers programming with Intel® Streaming SIMD Extensions (Intel® SSE), including move instructions (MOVHPS, MOVLHPS, MOVHLPS, MOVMSKPS) that transfer packed single precision floating-point values between memory and XMM registers or within XMM registers (affecting high/low quadwords while leaving others unchanged), and arithmetic instructions performing addition, subtraction, multiply, divide, reciprocal, square root, reciprocal of square root, and maximum operations on packed or scalar single precision floating-point values (e.g., ADDPS, SUBPS, ADDSS, SUBSS, MULPS, MULSS, DIVPS, DIVSS, RCPPS, RCPSS, SQRTPS, SQRTSS, RSQRTPS, RSQRTSS, MAXPS).",
        "key_terms": [
          "Intel® Streaming SIMD Extensions (Intel® SSE)",
          "MOVHPS",
          "MOVLHPS",
          "MOVHLPS",
          "MOVMSKPS",
          "packed single precision floating-point",
          "scalar single precision floating-point",
          "XMM register",
          "general-purpose register",
          "ADDPS",
          "SUBPS",
          "ADDSS",
          "SUBSS",
          "MULPS",
          "MULSS",
          "DIVPS",
          "DIVSS",
          "RCPPS",
          "RCPSS",
          "SQRTPS",
          "SQRTSS",
          "RSQRTPS",
          "RSQRTSS",
          "MAXPS"
        ],
        "source_pages": [
          260
        ],
        "children": [],
        "text_preview": "PROGRAMMING WITH INTEL® STREAMING SIMD EXTENSIONS (INTEL® SSE)\n\n\nThe MOVHPS (move high packed single precision floating-point) instruction moves two packed single precision\nfloating-point values from memory to the high quadword of an XMM register and vice versa. The low quadword of\nthe register is left unchanged.\nThe MOVLHPS (move packed single precision floating-point low to high) instruction moves two packed single preci-\nsion floating-point values from the low quadword of the source XMM register into the high quadword of the desti-\nnation XMM register. The low quadword of the destination register is left unchanged.\nThe MOVHLPS (move packed single precision floating-point high to low) instruction moves two packed single preci-\nsion floating-point values from the high quadword of the source XMM register into the low quadword of the desti-\nnation XMM register. The high quadword of the destination register is left unchanged.\nThe MOVMSKPS (move packed single precision floating-point mask) instruction transfers the most significant bit of\neach of the four packed single precision floating-point numbers in an XMM register to a general-purpose register.\nThis 4-bit value can then be used "
      },
      {
        "id": "leaf-323",
        "level": 0,
        "summary": "The XSAVE feature set manages state components, with XSAVE-enabled features (those with user state components) requiring XCR0 configuration; their registers are unmodified/instructions cause invalid-opcode exceptions (#UD) if XCR0 bits are clear. XSAVE is enabled only if CR4.OSXSAVE=1; if 0, XCR0 bits are treated as clear, blocking feature instructions. Some state components (x87, SSE, PT, PKRU, PASID, CET, HDC, UINTR, LBR, HWP) are XSAVE-managed but not XSAVE-enabled, allowing modification/execution regardless of CR4.OSXSAVE/XCR0. Enumeration of XSAVE support uses CPUID: CPUID.01H:ECX.XSAVE[26] indicates general XSAVE support (0: no XGETBV/XRSTOR/XSAVE/XSETBV or CPUID.0DH; 1: supports these instructions and CPUID.0DH). CPUID.0DH sub-leaves: 00H provides user state component bitmap (EDX:EAX), XSAVE area size for all components (ECX), and for current XCR0 bits (EBX); 01H: EAX[0] for XSAVEOPT support, EAX[1] for compaction extensions.",
        "key_terms": [
          "XSAVE feature set",
          "XCR0",
          "XSAVE-enabled",
          "CR4.OSXSAVE",
          "invalid-opcode exception (#UD)",
          "x87 state",
          "SSE state",
          "PT state",
          "PKRU state",
          "PASID state",
          "CET state",
          "HDC state",
          "UINTR state",
          "LBR state",
          "HWP state",
          "XSAVE-managed",
          "CPUID instruction",
          "CPUID.01H:ECX.XSAVE[26]",
          "XGETBV",
          "XRSTOR",
          "XRSTORS",
          "XSAVE",
          "XSAVEC",
          "XSAVEOPT",
          "XSAVES",
          "XSETBV",
          "CPUID.0DH",
          "sub-leaves",
          "user state components",
          "XSAVE area",
          "bitmap",
          "compaction extensions"
        ],
        "source_pages": [
          323
        ],
        "children": [],
        "text_preview": "MANAGING STATE USING THE XSAVE FEATURE SET\n\n\nSome XSAVE-supported features can be used only if XCR0 has been configured so that the features’ state compo-\nnents can be managed by the XSAVE feature set. (This applies only to features with user state components.) Such\nstate components and features are XSAVE-enabled. In general, the processor will not modify (or allow modifica-\ntion of) the registers of a state component of an XSAVE-enabled feature if the bit corresponding to that state\ncomponent is clear in XCR0. (If software clears such a bit in XCR0, the processor preserves the corresponding state\ncomponent.) If an XSAVE-enabled feature has not been fully enabled in XCR0, execution of any instruction defined\nfor that feature causes an invalid-opcode exception (#UD).\nAs will be explained in Section 13.3, the XSAVE feature set is enabled only if CR4.OSXSAVE[bit 18] = 1. If\nCR4.OSXSAVE = 0, the processor treats XSAVE-enabled state features and their state components as if all bits in\nXCR0 were clear; the state components cannot be modified and the features’ instructions cannot be executed.\nThe state components for x87 state, for SSE state, for PT state, for PKRU state, for PASID state"
      },
      {
        "id": "leaf-360",
        "level": 0,
        "summary": "This page continues Table 14-5, which details the promotion of Legacy SIMD ISA to 128-bit Arithmetic Intel® AVX Instructions. The table includes columns for VEX.256 Encoding (mostly 'no'), VEX.128 Encoding (mostly 'yes'), specific instructions, and reasons for not being promoted (e.g., 'VI', 'Scalar', 'Integer'). Relevant CPUID flags are also noted (e.g., CPUID.01H:ECX.SSSE3[9], SSE4_1[19], POPCNT[23], SSE4_2[20], PCLMULQDQ[1], AESNI[25]).",
        "key_terms": [
          "Legacy SIMD ISA",
          "128-Bit Arithmetic Intel® AVX Instructions",
          "VEX.256 Encoding",
          "VEX.128 Encoding",
          "Table 14-5",
          "CPUID.01H:ECX.SSSE3[9]",
          "CPUID.01H:ECX.SSE4_1[19]",
          "CPUID.01H:ECX.POPCNT[23]",
          "CPUID.01H:ECX.SSE4_2[20]",
          "CPUID.01H:ECX.PCLMULQDQ[1]",
          "CPUID.01H:ECX.AESNI[25]",
          "VI",
          "Scalar",
          "Integer",
          "PMADDWD",
          "PMADDUBSW",
          "PAVGB",
          "PAVGW",
          "PMULUDQ",
          "PCMPEQB",
          "PCMPEQW",
          "PCMPEQD",
          "PMULLW",
          "PMULHUW",
          "PMULHW",
          "PSUBSW",
          "PADDSW",
          "PSADBW",
          "PADDUSB",
          "PADDUSW",
          "PADDSB",
          "PSUBUSB",
          "PSUBUSW",
          "PSUBSB",
          "PMINUB",
          "PMINSW",
          "PMAXUB",
          "PMAXSW",
          "PADDB",
          "PADDW",
          "PADDD",
          "PADDQ",
          "PSUBB",
          "PSUBW",
          "PSUBD",
          "PSUBQ",
          "PSLLW",
          "PSLLD",
          "PSLLQ",
          "PSRAW",
          "PSRLW",
          "PSRLD",
          "PSRLQ",
          "PSRAD",
          "PHSUBW",
          "PHSUBD",
          "PHSUBSW",
          "PHADDW",
          "PHADDD",
          "PHADDSW",
          "PMULHRSW",
          "PSIGNB",
          "PSIGNW",
          "PSIGND",
          "PABSB",
          "PABSW",
          "PABSD",
          "DPPD",
          "PHMINPOSUW",
          "MPSADBW",
          "PMAXSB",
          "PMAXSD",
          "PMAXUD",
          "PMINSB",
          "PMINSD",
          "PMINUD",
          "PMAXUW",
          "PMINUW",
          "PMOVSXxx",
          "PMOVZXxx",
          "PMULDQ",
          "PMULLD",
          "ROUNDSD",
          "ROUNDSS",
          "POPCNT",
          "PCMPGTQ",
          "CRC32",
          "PCMPESTRI",
          "PCMPESTRM",
          "PCMPISTRI",
          "PCMPISTRM",
          "PCLMULQDQ"
        ],
        "source_pages": [
          360
        ],
        "children": [],
        "text_preview": "PROGRAMMING WITH INTEL® AVX, FMA, AND INTEL® AVX2\n\n\n          Table 14-5. Promotion of Legacy SIMD ISA to 128-Bit Arithmetic Intel® AVX Instructions (Contd.)\n      VEX.256           VEX.128\n                                                          Instruction                      Reason Not Promoted\n      Encoding          Encoding\n no               yes              PMADDWD, PMADDUBSW                                 VI\n no               yes              PAVGB, PAVGW, PMULUDQ                              VI\n no               yes              PCMPEQB, PCMPEQW, PCMPEQD                          VI\n no               yes              PMULLW, PMULHUW, PMULHW                            VI\n no               yes              PSUBSW, PADDSW, PSADBW                             VI\n no               yes              PADDUSB, PADDUSW, PADDSB                           VI\n no               yes              PSUBUSB, PSUBUSW, PSUBSB                           VI\n no               yes              PMINUB, PMINSW                                     VI\n no               yes              PMAXUB, PMAXSW                                     VI\n no               yes              PADDB, PADDW, PADDD, PADDQ    "
      },
      {
        "id": "leaf-361",
        "level": 0,
        "summary": "Covers promotion of legacy SIMD ISA to 128-bit Intel AVX arithmetic instructions (Table 14-5), noting AESDEC, AESDECLAST, AESENC, AESENCLAST, AESIMX, AESKEYGENASSIST have VEX.128 encoding (no VEX.256) with reason 'VI' (Vector Integer not promoted to 256-bit). Also details 128-bit non-arithmetic primitives in Intel AVX, including VEX-encoded instructions with same functionality as SIMD prefix-encoded XMM register instructions, plus enhancements (Table 14-6) like non-unit-strided fetching (broadcast, masked move), intra-register manipulation (permute), branch handling (variable blend with four-operand syntax, packed TEST for floating-point).",
        "key_terms": [
          "AESDEC",
          "AESDECLAST",
          "AESENC",
          "AESENCLAST",
          "AESIMX",
          "AESKEYGENASSIST",
          "VEX.256",
          "VEX.128",
          "VI (Vector Integer)",
          "non-arithmetic primitives",
          "VEX-prefix encoding",
          "SIMD prefixes",
          "128-bit data processing",
          "non-unit-strided fetching",
          "broadcast",
          "masked move",
          "intra-register manipulation",
          "permute",
          "branch handling",
          "variable blend instructions",
          "four-operand syntax",
          "packed TEST instructions",
          "XMM registers",
          "VBROADCASTSS",
          "VMASKMOVPS",
          "VMASKMOVPD"
        ],
        "source_pages": [
          361
        ],
        "children": [],
        "text_preview": "PROGRAMMING WITH INTEL® AVX, FMA, AND INTEL® AVX2\n\n\n          Table 14-5. Promotion of Legacy SIMD ISA to 128-Bit Arithmetic Intel® AVX Instructions (Contd.)\n      VEX.256            VEX.128\n                                                            Instruction                                Reason Not Promoted\n      Encoding           Encoding\n\n no                yes               AESDEC, AESDECLAST                                           VI\n no                yes               AESENC, AESENCLAST                                           VI\n no                yes               AESIMX, AESKEYGENASSIST                                      VI\n\nDescription of Column “Reason not promoted”:\n•     MMX: Instructions referencing MMX registers do not support VEX.\n•     Scalar: Scalar instructions are not promoted to 256-bit.\n•     Integer: Integer instructions are not promoted.\n•     VI: “Vector Integer” instructions are not promoted to 256-bit.\n\n\n\n14.2.4        Non-Arithmetic Primitives for 128-Bit Vector and Scalar Processing\nIntel AVX provides a full complement of data processing instructions that employ VEX-prefix encoding. These VEX-\nencoded instructions generally provide the same f"
      },
      {
        "id": "leaf-362",
        "level": 0,
        "summary": "The provided content includes details on 128-bit Intel® AVX instruction enhancements and the promotion status of legacy SIMD non-arithmetic ISA to VEX-128 encoding. Table 14-6 lists 128-bit Intel® AVX instruction enhancements such as VPERMILPD (two variants), VPERMILPS (two variants), VTESTPS, and VTESTPD, each with descriptions of their operations. It notes that 128-bit data processing instructions in AVX cover floating-point and integer data movement primitives. Legacy SIMD non-arithmetic ISA promoted to VEX-256 encoding also support VEX-128 encoding (see Table 14-3). Table 14-7 details the promotion status of remaining legacy SIMD non-arithmetic ISA to VEX-128 encoding, including VEX.256 and VEX.128 encoding status for various instructions and reasons for not being promoted (e.g., MMX, scalar, redundant, VI).",
        "key_terms": [
          "128-bit Intel® AVX Instruction Enhancement",
          "VPERMILPD",
          "VPERMILPS",
          "VTESTPS",
          "VTESTPD",
          "VEX-256 encoding",
          "VEX-128 encoding",
          "legacy SIMD non-arithmetic ISA",
          "Table 14-6",
          "Table 14-7",
          "data movement primitives",
          "floating-point",
          "integer"
        ],
        "source_pages": [
          362
        ],
        "children": [],
        "text_preview": "PROGRAMMING WITH INTEL® AVX, FMA, AND INTEL® AVX2\n\n\n                             Table 14-6. 128-Bit Intel® AVX Instruction Enhancement (Contd.)\n Instruction                              Description\n VPERMILPD xmm1, xmm2, xmm3/m128          Permute double precision floating-point values in xmm2 using controls from xmm3/mem\n                                          and store result in xmm1.\n VPERMILPD xmm1, xmm2/m128, imm8          Permute double precision floating-point values in xmm2/mem using controls from imm8\n                                          and store result in xmm1.\n VPERMILPS xmm1, xmm2, xmm3/m128          Permute single precision floating-point values in xmm2 using controls from xmm3/mem\n                                          and store result in xmm1.\n VPERMILPS xmm1, xmm2/m128, imm8          Permute single precision floating-point values in xmm2/mem using controls from imm8\n                                          and store result in xmm1.\n VTESTPS xmm1, xmm2/m128                  Set ZF if xmm2/mem AND xmm1 result is all 0s in packed single precision sign bits. Set CF\n                                          if xmm2/mem AND NOT xmm1 result is all 0s in packed"
      },
      {
        "id": "leaf-363",
        "level": 0,
        "summary": "The content includes a continuation of Table 14-7, which lists Legacy SIMD ISA instructions (e.g., PBLENDVB, PBLENDW, PEXTRW/B/D/Q, PINSRB/D/Q) promoted to 128-bit non-arithmetic Intel AVX instructions (VEX.256 encoding: no, VEX.128 encoding: yes) with 'VI' (Vector Integer) as the reason for not being promoted to 256-bit. Section 14.3 covers detection of Intel AVX instructions, requiring checks for OS support (CPUID.01H:ECX.OSXSAVE[27] = 1, XGETBV verifying XCR0[2:1] = '11b' for XMM/YMM state enable) and processor support (CPUID.01H:ECX.AVX[28] = 1), with a recommended sequence involving these steps.",
        "key_terms": [
          "Legacy SIMD ISA",
          "Intel AVX",
          "VEX.256 Encoding",
          "VEX.128 Encoding",
          "PBLENDVB",
          "PBLENDW",
          "PEXTRW",
          "PEXTRB",
          "PEXTRD",
          "PEXTRQ",
          "PINSRB",
          "PINSRD",
          "PINSRQ",
          "VI (Vector Integer)",
          "YMM register state",
          "XGETBV instruction",
          "XSAVE/XRSTOR",
          "CPUID.01H:ECX.OSXSAVE[27]",
          "XCR0[2:1] = '11b'",
          "CPUID.01H:ECX.AVX[28]"
        ],
        "source_pages": [
          363
        ],
        "children": [],
        "text_preview": "PROGRAMMING WITH INTEL® AVX, FMA, AND INTEL® AVX2\n\n\n       Table 14-7. Promotion of Legacy SIMD ISA to 128-Bit Non-Arithmetic Intel® AVX instruction (Contd.)\n     VEX.256            VEX.128\n                                                                Instruction                              Reason Not Promoted\n     Encoding           Encoding\n\nno                yes                  PBLENDVB, PBLENDW                                            VI\nno                yes                  PEXTRW, PEXTRB, PEXTRD, PEXTRQ                               VI\nno                yes                  PINSRB, PINSRD, PINSRQ                                       VI\n\nDescription of column “Reason not promoted”:\n•    MMX: Instructions referencing MMX registers do not support VEX.\n•    Scalar: Scalar instructions are not promoted to 256-bit.\n•    VI: “Vector Integer” instructions are not promoted to 256-bit.\n•    Note 1: MOVLPD/PS and MOVHPD/PS are not promoted to 256-bit. The equivalent functionality are provided\n     by VINSERTF128 and VEXTRACTF128 instructions as the existing instructions have no natural 256b extension\n•    Note 3: It is expected that using 128-bit INSERTPS followed by a VINSERTF1"
      },
      {
        "id": "leaf-364",
        "level": 0,
        "summary": "Describes the recommended process for detecting Intel® AVX instructions, including pseudocode for a supports_AVX() function. The process involves using CPUID to check OSXSAVE and AVX feature flags in ECX; if set, XGETBV (with ECX=0) is used to verify the operating system has enabled XMM and YMM state support by checking EAX after AND with 06H. A note warns against relying exclusively on CPUID.01H:ECX.AVX[28] or XSAVE[26], as these indicate hardware support only, not operating system support; without OS-enabled YMM state management, Intel AVX instructions will cause #UD. These steps also apply to enhanced 128-bit SIMD floating-point instructions in Intel AVX (using VEX prefix-encoding) operating on YMM states.",
        "key_terms": [
          "Intel® AVX",
          "detection process",
          "pseudocode",
          "supports_AVX()",
          "CPUID",
          "OSXSAVE",
          "AVX feature flags",
          "ECX",
          "XGETBV",
          "XMM state",
          "YMM state",
          "OS support",
          "hardware support",
          "#UD",
          "enhanced 128-bit SIMD floating-point instructions",
          "VEX prefix-encoding"
        ],
        "source_pages": [
          364
        ],
        "children": [],
        "text_preview": "PROGRAMMING WITH INTEL® AVX, FMA, AND INTEL® AVX2\n\n\nThe following pseudocode illustrates this recommended application Intel AVX detection process:\n\nExample 14-1. Detection of Intel® AVX Instruction\n\nINT supports_AVX()\n{ mov        eax, 1\n   cpuid\n   and       ecx, 018000000H\n   cmp       ecx, 018000000H; check both OSXSAVE and AVX feature flags\n    jne      not_supported\n   ; processor supports AVX instructions and XGETBV is enabled by OS\n   mov       ecx, 0; specify 0 for XCR0 register\n   XGETBV              ; result in EDX:EAX\n   and       eax, 06H\n   cmp       eax, 06H; check OS has enabled both XMM and YMM state support\n   jne       not_supported\n   mov       eax, 1\n   jmp       done\nNOT_SUPPORTED:\n   mov       eax, 0\n   done:\n}\n\n\n                                                          NOTE\n         It is unwise for an application to rely exclusively on CPUID.01H:ECX.AVX[28] or at all on\n         CPUID.01H:ECX.XSAVE[26]: These indicate hardware support but not operating system support. If\n         YMM state management is not enabled by an operating systems, Intel AVX instructions will #UD\n         regardless of CPUID.01H:ECX.AVX[28]. “CPUID.01H:ECX.XSAVE[26] = 1” does not gua"
      },
      {
        "id": "leaf-365",
        "level": 0,
        "summary": "This section covers detection sequences for VEX-encoded AES instructions (e.g., VAESDEC, VAESDECLAST, VAESENC, VAESENCLAST, VAESIMC, VAESKEYGENASSIST) and VPCLMULQDQ instructions. Detection of VEX-encoded AES instructions requires checking CPUID.01H:ECX.AES[25] = 1 and application support for Intel AVX, as demonstrated in Example 14-2, which includes CPUID checks for OSXSAVE, AVX, and AESNI feature flags, and using XGETBV to verify OS-enabled XMM and YMM state support. Similarly, detection of VEX-encoded VPCLMULQDQ requires checking CPUID.01H:ECX.PCLMULQDQ[1] = 1 and AVX support, shown in Example 14-3 with CPUID checks for OSXSAVE, AVX, and PCLMULQDQ feature flags, and XGETBV to confirm OS-enabled XMM and YMM state support.",
        "key_terms": [
          "VEX-encoded AES",
          "VPCLMULQDQ",
          "VAESDEC",
          "VAESDECLAST",
          "VAESENC",
          "VAESENCLAST",
          "VAESIMC",
          "VAESKEYGENASSIST",
          "YMM states",
          "CPUID",
          "Intel AVX",
          "XGETBV",
          "XMM states",
          "AESNI feature flag",
          "PCLMULQDQ feature flag",
          "XCR0 register",
          "OSXSAVE"
        ],
        "source_pages": [
          365
        ],
        "children": [],
        "text_preview": "PROGRAMMING WITH INTEL® AVX, FMA, AND INTEL® AVX2\n\n\n\n14.3.1      Detection of VEX-Encoded AES and VPCLMULQDQ\nThe VAESDEC/VAESDECLAST/VAESENC/VAESENCLAST/VAESIMC/VAESKEYGENASSIST instructions operate on\nYMM states. The detection sequence must combine checking for CPUID.01H:ECX.AES[25] = 1 and the sequence\nfor detection application support for Intel AVX.\n\nExample 14-2. Detection of VEX-Encoded Intel® AES-NI Instructions\n\nINT supports_VAESNI()\n{ mov        eax, 1\n   cpuid\n   and       ecx, 01A000000H\n   cmp       ecx, 01A000000H; check OSXSAVE AVX and AESNI feature flags\n    jne      not_supported\n   ; processor supports AVX and VEX-encoded AESNI and XGETBV is enabled by OS\n   mov       ecx, 0; specify 0 for XCR0 register\n   XGETBV              ; result in EDX:EAX\n   and       eax, 06H\n   cmp       eax, 06H; check OS has enabled both XMM and YMM state support\n   jne       not_supported\n   mov       eax, 1\n   jmp       done\nNOT_SUPPORTED:\n   mov       eax, 0\ndone:\n\n\nSimilarly, the detection sequence for VPCLMULQDQ must combine checking for CPUID.01H:ECX.PCLMULQDQ[1] =\n1 and the sequence for detection application support for Intel AVX.\nThis is shown in the pseudocode provided in Example"
      },
      {
        "id": "parent-0",
        "level": 1,
        "summary": "Intel® Streaming SIMD Extensions (SSE) is fully compatible with IA-32 processor software, enabling unmodified existing software execution on SSE-incorporating processors. It is detectable via CPUID and functional in all IA-32 execution modes (protected, real address, virtual-8086). The SSE programming environment includes eight 128-bit XMM registers (XMM0-XMM7) for packed/scalar single precision floating-point operations (64-bit mode adds eight more, XMM8-XMM15, via REX prefixes), independent of other registers. XMM registers cannot address memory (handled by general-purpose registers) but support loading/storing 32/64/128-bit data, with 128-bit stores using 16 consecutive bytes (low-order byte first). The 32-bit MXCSR register controls/statuses SIMD floating-point operations (SSE/SSE2/SSE3), featuring sticky exception flags (bits 0-5), exception mask bits (bits 7-12, all masked on power-up), rounding control (bits 13-14), Flush-to-zero (bit 15, non-IEEE 754 underflow handling), and Denormals-Are-Zeros (DAZ, bit 6, non-IEEE 754 denormal operand conversion, introduced in SSE2). MXCSR is loaded/stored via LDMXCSR/FXRSTOR and STMXCSR/FXSAVE, with bits 16-31 reserved (writing non-zero causes #GP). SSE state (XMM registers, MXCSR) is shared with SSE2/SSE3, enabling mixed instruction use without state saving, and XMM registers are independent of x87 FPU/MMX registers (parallel operations possible). SSE introduces a 128-bit packed single precision floating-point data type (four 32-bit IEEE values). Key instructions include data movement (e.g., MOVAPS for aligned 128-bit transfers, MOVUPS for unaligned, MOVSS for scalar low doubleword, MOVLPS/MOVHPS for quadword transfers) and arithmetic operations (e.g., ADDPS/SUBPS for packed addition/subtraction, ADDSS/SUBSS for scalar, MULPS/MULSS, DIVPS/DIVSS, reciprocal (RCPPS/RCPSS), square root (SQRTPS/SQRTSS), reciprocal square root (RSQRTPS/RSQRTSS), MAXPS). Packed operations act on all four doublewords of operands, while scalar operations target only the low doubleword (X0/Y0), differing from x87 FPU in exponent range (8-bit vs. x87's 15-bit).",
        "key_relationships": {
          "XMM Registers": "Primary storage for packed/scalar single precision floating-point operands; cannot address memory (memory addressing via general-purpose registers); 8 base registers (XMM0-XMM7) in IA-32 modes, 16 (XMM8-XMM15 added) in 64-bit mode via REX prefixes.",
          "MXCSR Register": "Controls SIMD floating-point operations (SSE/SSE2/SSE3) via exception flags (bits 0-5), mask bits (7-12), rounding control (13-14), Flush-to-zero (15), and DAZ (6); loaded/stored via LDMXCSR/FXRSTOR and STMXCSR/FXSAVE; reserved bits (16-31) cause #GP on non-zero writes.",
          "Data Types": "128-bit packed single precision floating-point (four 32-bit IEEE values) is the core SSE data type, operated on in XMM registers/memory with 32/64/128-bit load/store increments (128-bit stores use 16-byte low-order-first alignment).",
          "Instruction Groups": "SSE instructions include data movement (e.g., MOVAPS/MOVUPS for aligned/unaligned 128-bit transfers, MOVSS for scalar) and arithmetic (e.g., ADDPS/ADDSS for packed/scalar addition, RCPPS for reciprocal, SQRTPS for square root); packed operations act on all four doublewords, scalar on low doubleword.",
          "Compatibility": "SSE state (XMM, MXCSR) is shared with SSE2/SSE3, allowing mixed instruction use; XMM registers are independent of x87 FPU/MMX registers (parallel operations possible); 64-bit mode extends XMM registers and uses REX prefixes for memory operands."
        },
        "source_pages": [
          254,
          255,
          256,
          257,
          258,
          259,
          260
        ],
        "children": [
          "leaf-254",
          "leaf-255",
          "leaf-256",
          "leaf-257",
          "leaf-258",
          "leaf-259",
          "leaf-260"
        ]
      },
      {
        "id": "parent-1",
        "level": 1,
        "summary": "Pages 360-365 detail the promotion of Legacy SIMD ISA to 128-bit Intel AVX instructions (arithmetic and non-arithmetic), 128-bit non-arithmetic AVX enhancements, and detection processes for AVX, VEX-encoded AES, and VPCLMULQDQ. Table 14-5 covers 128-bit arithmetic promotion: most have VEX.128 (yes) and VEX.256 (no), with reasons like 'VI' (Vector Integer), 'Scalar', or 'Integer'; includes AES instructions (e.g., AESDEC) with 'VI' as 256-bit promotion reason. 128-bit non-arithmetic AVX primitives (Table 14-6) offer same functionality as SIMD prefix-encoded XMM instructions plus enhancements (broadcast, masked move, permute, branch handling like variable blend or packed TEST for floating-point). Table 14-7 details remaining non-arithmetic promotion: instructions (e.g., PBLENDVB, PEXTRW) have VEX.128 (yes), VEX.256 (no), with reasons like 'VI', 'MMX', or 'redundant'. Legacy non-arithmetic ISA promoted to VEX-256 also support VEX-128 (Table 14-3). AVX detection requires CPU support (CPUID.01H:ECX.AVX[28] = 1) and OS support (CPUID.01H:ECX.OSXSAVE[27] = 1, XGETBV verifying XCR0[2:1] = '11b'). VEX-encoded AES and VPCLMULQDQ detection build on AVX detection, requiring their specific CPUID flags (AESNI[25] for AES, PCLMULQDQ[1] for VPCLMULQDQ) plus OS-enabled XMM/YMM state via XGETBV.",
        "key_relationships": {
          "Tables": "Table 14-5 (arithmetic promotion), Table 14-6 (128-bit non-arithmetic enhancements), Table 14-7 (remaining non-arithmetic promotion) are core; Table 14-3 notes VEX-256 promoted non-arithmetic ISA also support VEX-128.",
          "Promotion Reasons": "'VI' (Vector Integer) is a common reason for 256-bit non-promotion across arithmetic (Table 14-5) and non-arithmetic (Table 14-7) instructions.",
          "AVX Detection": "Requires both CPU support (CPUID.01H:ECX.AVX[28]) and OS support (OSXSAVE flag + XGETBV XCR0[2:1] = '11b') to avoid #UD.",
          "AES/VPCLMULQDQ Detection": "Build on AVX detection, adding their specific CPUID flags (AESNI[25] for AES, PCLMULQDQ[1] for VPCLMULQDQ) while retaining OS support checks via XGETBV."
        },
        "source_pages": [
          360,
          361,
          362,
          363,
          364,
          365
        ],
        "children": [
          "leaf-360",
          "leaf-361",
          "leaf-362",
          "leaf-363",
          "leaf-364",
          "leaf-365"
        ]
      },
      {
        "id": "parent-2",
        "level": 1,
        "summary": "The XSAVE feature set manages state components, distinguishing between XSAVE-enabled (requiring XCR0 configuration) and XSAVE-managed (non-XSAVE-enabled) components. XSAVE-enabled features have user state components; their registers remain unmodified and instructions cause invalid-opcode exceptions (#UD) if XCR0 bits are clear. XSAVE is enabled only when CR4.OSXSAVE=1; if CR4.OSXSAVE=0, XCR0 bits are treated as clear, blocking XSAVE-enabled feature instructions. XSAVE-managed but non-XSAVE-enabled components (x87, SSE, PT, PKRU, PASID, CET, HDC, UINTR, LBR, HWP) allow modification/execution regardless of CR4.OSXSAVE/XCR0. Enumeration uses CPUID: CPUID.01H:ECX.XSAVE[26] indicates general XSAVE support (1=supports XGETBV/XRSTOR/XSAVE/XSETBV and CPUID.0DH; 0=does not). CPUID.0DH sub-leaves: 00H provides user state component bitmap (EDX:EAX), XSAVE area size for all components (ECX), and current XCR0 bits size (EBX); 01H: EAX[0] for XSAVEOPT support, EAX[1] for compaction extensions.",
        "key_relationships": [
          "XSAVE-enabled features require XCR0 configuration; XCR0 bits clear → registers unmodified/instructions cause #UD",
          "XSAVE enabled only if CR4.OSXSAVE=1; CR4.OSXSAVE=0 → XCR0 bits treated as clear, blocking XSAVE-enabled instructions",
          "XSAVE-managed non-enabled components (x87, SSE, etc.) modified/executed regardless of CR4.OSXSAVE/XCR0",
          "CPUID.01H:ECX.XSAVE[26] = 1 → supports XGETBV/XRSTOR/XSAVE/XSETBV and CPUID.0DH",
          "CPUID.0DH sub-leaf 00H → user state bitmap (EDX:EAX), XSAVE area size (all components: ECX; current XCR0 bits: EBX)",
          "CPUID.0DH sub-leaf 01H: EAX[0] = XSAVEOPT support; EAX[1] = compaction extensions"
        ],
        "source_pages": [
          323
        ],
        "children": [
          "leaf-323"
        ]
      },
      {
        "id": "root",
        "level": 2,
        "summary": "The content covers key components of Intel's SIMD (Single Instruction, Multiple Data) architecture and state management, including the Streaming SIMD Extensions (SSE) as a foundational SIMD extension, the promotion of legacy SIMD ISA to 128-bit Intel AVX (Advanced Vector Extensions) instructions, and the XSAVE feature set for managing state components of these extensions.",
        "major_themes": [
          "Intel Streaming SIMD Extensions (SSE) architecture and programming environment",
          "Promotion of legacy SIMD ISA to 128-bit Intel AVX instructions",
          "XSAVE feature set for state component management"
        ],
        "source_pages": [
          254,
          255,
          256,
          257,
          258,
          259,
          260,
          323,
          360,
          361,
          362,
          363,
          364,
          365
        ],
        "children": [
          "parent-0",
          "parent-1",
          "parent-2"
        ]
      }
    ],
    "statistics": {
      "levels": 3,
      "leaves": 14,
      "parents": 3,
      "roots": 1
    }
  },
  "graphrag": {
    "build_latency_ms": 789159.331,
    "entities": {
      "intel_streaming_simd_extensions_intel_sse": {
        "id": "intel_streaming_simd_extensions_intel_sse",
        "name": "Intel® Streaming SIMD Extensions (Intel® SSE)",
        "type": "Instruction Set Extension",
        "descriptions": [
          "A SIMD extension compatible with IA-32 software, accessible in IA-32 execution modes, with a programming environment including registers, data types, and instructions."
        ],
        "evidence": [
          {
            "page": 254,
            "quote": "Intel SSE is fully compatible with all software written for IA-32 processors... Intel SSE is accessible from all IA-32 execution modes: protected mode, real address mode, and virtual-8086 mode."
          }
        ],
        "source_pages": [
          254
        ]
      },
      "ia_32_processors": {
        "id": "ia_32_processors",
        "name": "IA-32 processors",
        "type": "Processor Architecture",
        "descriptions": [
          "Processors for which Intel SSE is compatible, allowing existing software to run unmodified."
        ],
        "evidence": [
          {
            "page": 254,
            "quote": "Intel SSE is fully compatible with all software written for IA-32 processors. All existing software continues to run correctly, without modification, on processors that incorporate Intel SSE."
          }
        ],
        "source_pages": [
          254
        ]
      },
      "ia_32_execution_modes": {
        "id": "ia_32_execution_modes",
        "name": "IA-32 execution modes",
        "type": "Execution Mode",
        "descriptions": [
          "Modes (protected, real address, virtual-8086) from which Intel SSE is accessible."
        ],
        "evidence": [
          {
            "page": 254,
            "quote": "Intel SSE is accessible from all IA-32 execution modes: protected mode, real address mode, and virtual-8086 mode."
          }
        ],
        "source_pages": [
          254
        ]
      },
      "protected_mode": {
        "id": "protected_mode",
        "name": "protected mode",
        "type": "Execution Mode",
        "descriptions": [
          "One of the IA-32 execution modes from which Intel SSE is accessible."
        ],
        "evidence": [
          {
            "page": 254,
            "quote": "Intel SSE is accessible from all IA-32 execution modes: protected mode, real address mode, and virtual-8086 mode."
          }
        ],
        "source_pages": [
          254
        ]
      },
      "real_address_mode": {
        "id": "real_address_mode",
        "name": "real address mode",
        "type": "Execution Mode",
        "descriptions": [
          "One of the IA-32 execution modes from which Intel SSE is accessible."
        ],
        "evidence": [
          {
            "page": 254,
            "quote": "Intel SSE is accessible from all IA-32 execution modes: protected mode, real address mode, and virtual-8086 mode."
          }
        ],
        "source_pages": [
          254
        ]
      },
      "virtual_8086_mode": {
        "id": "virtual_8086_mode",
        "name": "virtual-8086 mode",
        "type": "Execution Mode",
        "descriptions": [
          "One of the IA-32 execution modes from which Intel SSE is accessible."
        ],
        "evidence": [
          {
            "page": 254,
            "quote": "Intel SSE is accessible from all IA-32 execution modes: protected mode, real address mode, and virtual-8086 mode."
          }
        ],
        "source_pages": [
          254
        ]
      },
      "intel_sse_programming_environment": {
        "id": "intel_sse_programming_environment",
        "name": "Intel® SSE Programming Environment",
        "type": "Programming Environment",
        "descriptions": [
          "The execution environment for Intel SSE, including registers, data types, and instructions."
        ],
        "evidence": [
          {
            "page": 254,
            "quote": "The following sections of this chapter describe the programming environment for Intel SSE, including: XMM registers, the packed single precision floating-point data type, and Intel SSE instructions."
          }
        ],
        "source_pages": [
          254
        ]
      },
      "xmm_registers": {
        "id": "xmm_registers",
        "name": "XMM registers",
        "type": "Register",
        "descriptions": [
          "Eight 128-bit registers used to operate on packed or scalar single precision floating-point data, referenced as XMM0 through XMM7.",
          "Eight 128-bit data registers (XMM0 to XMM7) introduced with Intel SSE; not aliased to other registers; used for packed single precision floating-point operands (SSE), expanded by SSE2 for double precision floating-point and packed integer operands; cannot address memory; data loaded/stored in 32-bit, 64-bit, and 128-bit increments",
          "128-bit registers for SSE/SSE2/SSE3; independent of x87/MMX",
          "Used to operate on 128-bit packed single precision floating-point data types",
          "Used for moving single precision floating-point data in Intel SSE operations"
        ],
        "evidence": [
          {
            "page": 254,
            "quote": "XMM registers — These eight registers... are used to operate on packed or scalar single precision floating-point data... XMM registers are referenced by the names XMM0 through XMM7."
          },
          {
            "page": 255,
            "quote": "Eight 128-bit XMM data registers were introduced into the IA-32 architecture with Intel SSE (see Figure 10-2). These registers can be accessed directly using the names XMM0 to XMM7; and they can be accessed independently from the x87 FPU and MMX registers and the general-purpose registers (that is, they are not aliased to any other of the processor’s registers). Intel SSE instructions use the XMM registers only to operate on packed single precision floating-point operands. SSE2 extensions expand the functions of the XMM registers to operand on packed or scalar double precision floating-point operands and packed integer operands; ... XMM registers can only be used to perform calculations on data; they cannot be used to address memory. Data can be loaded into XMM registers or written from the registers to memory in 32-bit, 64-bit, and 128-bit increments."
          }
        ],
        "source_pages": [
          254,
          255,
          257,
          258,
          259
        ]
      },
      "mxcsr_register": {
        "id": "mxcsr_register",
        "name": "MXCSR register",
        "type": "Register",
        "descriptions": [
          "A 32-bit register providing status and control bits for SIMD floating-point operations.",
          "Control/status register for SIMD floating-point ops with reserved bits 16-31",
          "Register with flags like DAZ; controls SIMD floating-point behavior"
        ],
        "evidence": [
          {
            "page": 254,
            "quote": "MXCSR register — This 32-bit register... provides status and control bits used in SIMD floating-point operations."
          }
        ],
        "source_pages": [
          254,
          256,
          257
        ]
      },
      "mmx_registers": {
        "id": "mmx_registers",
        "name": "MMX registers",
        "type": "Register",
        "descriptions": [
          "Eight 64-bit registers used for 64-bit packed integer data operations and operands between MMX and XMM registers, referenced as MM0 through MM7.",
          "Involved in conversion instructions with XMM registers"
        ],
        "evidence": [
          {
            "page": 254,
            "quote": "MMX registers — These eight registers... are used to perform operations on 64-bit packed integer data. They are also used to hold operands for some operations performed between the MMX and XMM registers. MMX registers are referenced by the names MM0 through MM7."
          }
        ],
        "source_pages": [
          254,
          258
        ]
      },
      "general_purpose_registers": {
        "id": "general_purpose_registers",
        "name": "General-purpose registers",
        "type": "Register",
        "descriptions": [
          "Eight 32-bit registers used with IA-32 addressing modes to address memory operands.",
          "Used to hold operands for some SSE instructions and address memory; includes EAX, EBX, ECX, EDX, EBP, ESI, EDI, ESP"
        ],
        "evidence": [
          {
            "page": 254,
            "quote": "General-purpose registers — The eight general-purpose registers... are used along with the existing IA-32 addressing modes to address operands in memory."
          },
          {
            "page": 255,
            "quote": "The general-purpose registers are also used to hold operands for some SSE instructions and are referenced as EAX, EBX, ECX, EDX, EBP, ESI, EDI, and ESP."
          }
        ],
        "source_pages": [
          254,
          255
        ]
      },
      "packed_single_precision_floating_point_data_type": {
        "id": "packed_single_precision_floating_point_data_type",
        "name": "packed single precision floating-point data type",
        "type": "Data Type",
        "descriptions": [
          "A data type operated on by XMM registers in the Intel SSE programming environment."
        ],
        "evidence": [
          {
            "page": 254,
            "quote": "the programming environment for Intel SSE, including: XMM registers, the packed single precision floating-point data type, and Intel SSE instructions."
          }
        ],
        "source_pages": [
          254
        ]
      },
      "intel_sse_instructions": {
        "id": "intel_sse_instructions",
        "name": "Intel SSE instructions",
        "type": "Instruction Set",
        "descriptions": [
          "Instructions part of the Intel SSE programming environment.",
          "Instructions that use XMM registers to operate on packed single precision floating-point operands; some may operate on general-purpose registers"
        ],
        "evidence": [
          {
            "page": 254,
            "quote": "the programming environment for Intel SSE, including: XMM registers, the packed single precision floating-point data type, and Intel SSE instructions."
          },
          {
            "page": 255,
            "quote": "Intel SSE instructions use the XMM registers only to operate on packed single precision floating-point operands... Some Intel SSE instructions may be used to operate on general-purpose registers."
          }
        ],
        "source_pages": [
          254,
          255
        ]
      },
      "64_bit_packed_integer_data": {
        "id": "64_bit_packed_integer_data",
        "name": "64-bit packed integer data",
        "type": "Data Type",
        "descriptions": [
          "A data type operated on by MMX registers."
        ],
        "evidence": [
          {
            "page": 254,
            "quote": "MMX registers... are used to perform operations on 64-bit packed integer data."
          }
        ],
        "source_pages": [
          254
        ]
      },
      "ia_32_addressing_modes": {
        "id": "ia_32_addressing_modes",
        "name": "IA-32 addressing modes",
        "type": "Addressing Mode",
        "descriptions": [
          "Addressing modes used with general-purpose registers to address memory operands."
        ],
        "evidence": [
          {
            "page": 254,
            "quote": "General-purpose registers... are used along with the existing IA-32 addressing modes to address operands in memory."
          }
        ],
        "source_pages": [
          254
        ]
      },
      "memory_operands": {
        "id": "memory_operands",
        "name": "memory operands",
        "type": "Operand",
        "descriptions": [
          "Operands in memory addressed by general-purpose registers and IA-32 addressing modes."
        ],
        "evidence": [
          {
            "page": 254,
            "quote": "General-purpose registers... are used along with the existing IA-32 addressing modes to address operands in memory."
          }
        ],
        "source_pages": [
          254
        ]
      },
      "simd_floating_point_operations": {
        "id": "simd_floating_point_operations",
        "name": "SIMD floating-point operations",
        "type": "Operation",
        "descriptions": [
          "Floating-point operations controlled by the MXCSR register's status and control bits."
        ],
        "evidence": [
          {
            "page": 254,
            "quote": "MXCSR register... provides status and control bits used in SIMD floating-point operations."
          }
        ],
        "source_pages": [
          254
        ]
      },
      "eflags_register": {
        "id": "eflags_register",
        "name": "EFLAGS register",
        "type": "Register",
        "descriptions": [
          "32-bit register used to record result of some compare operations"
        ],
        "evidence": [
          {
            "page": 255,
            "quote": "EFLAGS register — This 32-bit register (see Figure 3-7) is used to record result of some compare operations."
          }
        ],
        "source_pages": [
          255
        ]
      },
      "64_bit_mode": {
        "id": "64_bit_mode",
        "name": "64-bit mode",
        "type": "Processor Mode",
        "descriptions": [
          "Mode where Intel SSE has eight additional XMM registers (XMM8-XMM15) accessible via REX prefixes; memory operands use ModR/M, SIB encoding"
        ],
        "evidence": [
          {
            "page": 255,
            "quote": "In 64-bit mode, eight additional XMM registers are accessible. Registers XMM8-XMM15 are accessed by using REX prefixes. Memory operands are specified using the ModR/M, SIB encoding described in Section 3.7.5."
          }
        ],
        "source_pages": [
          255
        ]
      },
      "compatibility_mode": {
        "id": "compatibility_mode",
        "name": "Compatibility mode",
        "type": "Processor Mode",
        "descriptions": [
          "Mode where Intel SSE functions like it does in protected mode"
        ],
        "evidence": [
          {
            "page": 255,
            "quote": "In compatibility mode, Intel SSE functions like it does in protected mode."
          }
        ],
        "source_pages": [
          255
        ]
      },
      "rex_prefixes": {
        "id": "rex_prefixes",
        "name": "REX prefixes",
        "type": "Instruction Prefix",
        "descriptions": [
          "Prefixes used to access XMM8-XMM15 registers in 64-bit mode and 64-bit general-purpose registers; ignored if used when meaningless"
        ],
        "evidence": [
          {
            "page": 255,
            "quote": "Registers XMM8-XMM15 are accessed by using REX prefixes... Use the REX.W prefix to access 64-bit general-purpose registers. Note that if a REX prefix is used when it has no meaning, the prefix is ignored."
          }
        ],
        "source_pages": [
          255
        ]
      },
      "mxcsr_control_and_status_register": {
        "id": "mxcsr_control_and_status_register",
        "name": "MXCSR Control and Status Register",
        "type": "Control Register",
        "descriptions": [
          "32-bit register containing control and status information for Intel SSE, SSE2, and SSE3 SIMD floating-point operations; includes flag and mask bits for SIMD floating-point exceptions and rounding control field for SIMD floating-point operations"
        ],
        "evidence": [
          {
            "page": 255,
            "quote": "The 32-bit MXCSR register (see Figure 10-3) contains control and status information for Intel SSE, SSE2, and SSE3 SIMD floating-point operations. This register contains: • Flag and mask bits for SIMD floating-point exceptions. • Rounding control field for SIMD floating-point operations."
          }
        ],
        "source_pages": [
          255
        ]
      },
      "sse2_extensions": {
        "id": "sse2_extensions",
        "name": "SSE2 extensions",
        "type": "Instruction Set Extension",
        "descriptions": [
          "Extensions that expand the functions of the XMM registers to operand on packed or scalar double precision floating-point operands and packed integer operands"
        ],
        "evidence": [
          {
            "page": 255,
            "quote": "SSE2 extensions expand the functions of the XMM registers to operand on packed or scalar double precision floating-point operands and packed integer operands"
          }
        ],
        "source_pages": [
          255
        ]
      },
      "memory_addressing": {
        "id": "memory_addressing",
        "name": "memory addressing",
        "type": "concept",
        "descriptions": [],
        "evidence": [],
        "source_pages": [
          255
        ]
      },
      "compare_operations": {
        "id": "compare_operations",
        "name": "compare operations",
        "type": "concept",
        "descriptions": [],
        "evidence": [],
        "source_pages": [
          255
        ]
      },
      "xmm8_xmm15": {
        "id": "xmm8_xmm15",
        "name": "XMM8-XMM15",
        "type": "concept",
        "descriptions": [],
        "evidence": [],
        "source_pages": [
          255
        ]
      },
      "64_bit_general_purpose_registers": {
        "id": "64_bit_general_purpose_registers",
        "name": "64-bit general-purpose registers",
        "type": "concept",
        "descriptions": [],
        "evidence": [],
        "source_pages": [
          255
        ]
      },
      "intel_sse": {
        "id": "intel_sse",
        "name": "Intel SSE",
        "type": "concept",
        "descriptions": [],
        "evidence": [],
        "source_pages": [
          255
        ]
      },
      "sse2": {
        "id": "sse2",
        "name": "SSE2",
        "type": "concept",
        "descriptions": [],
        "evidence": [],
        "source_pages": [
          255
        ]
      },
      "sse3": {
        "id": "sse3",
        "name": "SSE3",
        "type": "concept",
        "descriptions": [],
        "evidence": [],
        "source_pages": [
          255
        ]
      },
      "flush_to_zero_flag": {
        "id": "flush_to_zero_flag",
        "name": "Flush-to-zero flag",
        "type": "Flag",
        "descriptions": [
          "Bit 15 of MXCSR; controls masked underflow response in SIMD floating-point ops"
        ],
        "evidence": [],
        "source_pages": [
          256
        ]
      },
      "denormals_are_zeros_flag": {
        "id": "denormals_are_zeros_flag",
        "name": "Denormals-are-zeros flag",
        "type": "Flag",
        "descriptions": [
          "Controls handling of denormal source operands in SIMD floating-point instructions"
        ],
        "evidence": [],
        "source_pages": [
          256
        ]
      },
      "ldmxcsr_instruction": {
        "id": "ldmxcsr_instruction",
        "name": "LDMXCSR instruction",
        "type": "Instruction",
        "descriptions": [
          "Loads MXCSR contents from memory; clears exception flags when writing zeros"
        ],
        "evidence": [],
        "source_pages": [
          256
        ]
      },
      "fxrstor_instruction": {
        "id": "fxrstor_instruction",
        "name": "FXRSTOR instruction",
        "type": "Instruction",
        "descriptions": [
          "Loads MXCSR contents from memory; writing non-zero reserved bits causes #GP",
          "Restores SSE/SSE2/SSE3, x87 FPU, and MMX state"
        ],
        "evidence": [],
        "source_pages": [
          256,
          257
        ]
      },
      "stmxcsr_instruction": {
        "id": "stmxcsr_instruction",
        "name": "STMXCSR instruction",
        "type": "Instruction",
        "descriptions": [
          "Stores MXCSR register contents from processor to memory"
        ],
        "evidence": [],
        "source_pages": [
          256
        ]
      },
      "fxsave_instruction": {
        "id": "fxsave_instruction",
        "name": "FXSAVE instruction",
        "type": "Instruction",
        "descriptions": [
          "Stores MXCSR contents to memory; writing non-zero reserved bits causes #GP",
          "Saves SSE/SSE2/SSE3, x87 FPU, and MMX state"
        ],
        "evidence": [],
        "source_pages": [
          256,
          257
        ]
      },
      "simd_floating_point_exceptions": {
        "id": "simd_floating_point_exceptions",
        "name": "SIMD floating-point exceptions",
        "type": "Exception",
        "descriptions": [
          "Detected by MXCSR bits 0-5; sticky flags remain set until cleared"
        ],
        "evidence": [],
        "source_pages": [
          256
        ]
      },
      "general_protection_exception_#gp": {
        "id": "general_protection_exception_#gp",
        "name": "general-protection exception (#GP)",
        "type": "concept",
        "descriptions": [
          "Generated by MOVAPS if memory address not 16-byte aligned"
        ],
        "evidence": [],
        "source_pages": [
          256,
          259
        ]
      },
      "flush_to_zero_mode": {
        "id": "flush_to_zero_mode",
        "name": "flush-to-zero mode",
        "type": "Processor Mode",
        "descriptions": [
          "Rounds underflow results to zero for performance; not IEEE 754 compatible"
        ],
        "evidence": [],
        "source_pages": [
          257
        ]
      },
      "denormals_are_zeros_mode_daz": {
        "id": "denormals_are_zeros_mode_daz",
        "name": "denormals-are-zeros mode (DAZ)",
        "type": "Processor Mode",
        "descriptions": [
          "Converts denormal operands to zero with original sign; improves streaming media performance"
        ],
        "evidence": [],
        "source_pages": [
          257
        ]
      },
      "ieee_standard_754": {
        "id": "ieee_standard_754",
        "name": "IEEE Standard 754",
        "type": "Standard",
        "descriptions": [
          "Floating-point standard; mandates denormal result on underflow"
        ],
        "evidence": [],
        "source_pages": [
          257
        ]
      },
      "128_bit_packed_single_precision_floating_point_data_type": {
        "id": "128_bit_packed_single_precision_floating_point_data_type",
        "name": "128-bit packed single precision floating-point data type",
        "type": "Data Type",
        "descriptions": [
          "SSE data type with four 32-bit single precision floats packed in 128 bits",
          "Operated on in XMM registers or memory; contains 4 single precision values"
        ],
        "evidence": [],
        "source_pages": [
          257,
          258
        ]
      },
      "sse_sse2_sse3": {
        "id": "sse_sse2_sse3",
        "name": "SSE/SSE2/SSE3",
        "type": "concept",
        "descriptions": [],
        "evidence": [],
        "source_pages": [
          257
        ]
      },
      "x87_fpu_mmx_registers": {
        "id": "x87_fpu_mmx_registers",
        "name": "x87 FPU/MMX registers",
        "type": "concept",
        "descriptions": [],
        "evidence": [],
        "source_pages": [
          257
        ]
      },
      "intel_sse_instruction_set": {
        "id": "intel_sse_instruction_set",
        "name": "Intel SSE instruction set",
        "type": "Instruction Set",
        "descriptions": [
          "Divided into four functional groups: packed/scalar FP, 64-bit SIMD integer, state management, cacheability control"
        ],
        "evidence": [],
        "source_pages": [
          258
        ]
      },
      "packed_and_scalar_single_precision_floating_point_instructions": {
        "id": "packed_and_scalar_single_precision_floating_point_instructions",
        "name": "Packed and scalar single precision floating-point instructions",
        "type": "Instruction Subgroup",
        "descriptions": [
          "Subgroup of Intel SSE instruction set; includes data movement, arithmetic, logical, comparison, shuffle, conversion instructions"
        ],
        "evidence": [],
        "source_pages": [
          258
        ]
      },
      "movups_instruction": {
        "id": "movups_instruction",
        "name": "MOVUPS instruction",
        "type": "Instruction",
        "descriptions": [
          "Supports unaligned accesses for 128-bit packed memory operands",
          "Transfers four packed single precision floating-point values; no 16-byte alignment required"
        ],
        "evidence": [],
        "source_pages": [
          258,
          259
        ]
      },
      "data_movement_instructions": {
        "id": "data_movement_instructions",
        "name": "Data movement instructions",
        "type": "Instruction Subtype",
        "descriptions": [
          "Subgroup of packed and scalar single precision floating-point instructions"
        ],
        "evidence": [],
        "source_pages": [
          258
        ]
      },
      "arithmetic_instructions": {
        "id": "arithmetic_instructions",
        "name": "Arithmetic instructions",
        "type": "Instruction Subtype",
        "descriptions": [
          "Subgroup of packed and scalar single precision floating-point instructions"
        ],
        "evidence": [],
        "source_pages": [
          258
        ]
      },
      "64_bit_simd_integer_instructions": {
        "id": "64_bit_simd_integer_instructions",
        "name": "64-bit SIMD integer instructions",
        "type": "concept",
        "descriptions": [],
        "evidence": [],
        "source_pages": [
          258
        ]
      },
      "conversion_instructions": {
        "id": "conversion_instructions",
        "name": "Conversion instructions",
        "type": "concept",
        "descriptions": [],
        "evidence": [],
        "source_pages": [
          258
        ]
      },
      "movaps_instruction": {
        "id": "movaps_instruction",
        "name": "MOVAPS instruction",
        "type": "Data Movement Instruction",
        "descriptions": [
          "Transfers four packed single precision floating-point values; requires 16-byte aligned memory address"
        ],
        "evidence": [],
        "source_pages": [
          259
        ]
      },
      "movss_instruction": {
        "id": "movss_instruction",
        "name": "MOVSS instruction",
        "type": "Data Movement Instruction",
        "descriptions": [
          "Transfers 32-bit scalar single precision floating-point value between XMM registers and memory"
        ],
        "evidence": [],
        "source_pages": [
          259
        ]
      },
      "movlps_instruction": {
        "id": "movlps_instruction",
        "name": "MOVLPS instruction",
        "type": "Data Movement Instruction",
        "descriptions": [
          "Moves two packed single precision floating-point values to low quadword of XMM register"
        ],
        "evidence": [],
        "source_pages": [
          259
        ]
      },
      "scalar_single_precision_floating_point_instructions": {
        "id": "scalar_single_precision_floating_point_instructions",
        "name": "Scalar single precision floating-point instructions",
        "type": "Instruction",
        "descriptions": [
          "Operate on low doublewords (X0, Y0); higher doublewords passed through to destination"
        ],
        "evidence": [],
        "source_pages": [
          259
        ]
      },
      "packed_single_precision_floating_point_operations": {
        "id": "packed_single_precision_floating_point_operations",
        "name": "Packed single precision floating-point operations",
        "type": "Operation",
        "descriptions": [
          "Perform OP on X3/Y3, X2/Y2, X1/Y1, X0/Y0 doublewords"
        ],
        "evidence": [],
        "source_pages": [
          259
        ]
      },
      "x0_y0": {
        "id": "x0_y0",
        "name": "X0/Y0",
        "type": "concept",
        "descriptions": [],
        "evidence": [],
        "source_pages": [
          259
        ]
      },
      "x3_y3_x2_y2_x1_y1_x0_y0": {
        "id": "x3_y3_x2_y2_x1_y1_x0_y0",
        "name": "X3/Y3, X2/Y2, X1/Y1, X0/Y0",
        "type": "concept",
        "descriptions": [],
        "evidence": [],
        "source_pages": [
          259
        ]
      },
      "intel_sse_data_movement_instructions": {
        "id": "intel_sse_data_movement_instructions",
        "name": "Intel SSE data movement instructions",
        "type": "concept",
        "descriptions": [],
        "evidence": [],
        "source_pages": [
          259
        ]
      },
      "xmm_register": {
        "id": "xmm_register",
        "name": "XMM register",
        "type": "Register",
        "descriptions": [
          "Register used for storing packed single precision floating-point values in Intel SSE instructions"
        ],
        "evidence": [],
        "source_pages": [
          260
        ]
      },
      "general_purpose_register": {
        "id": "general_purpose_register",
        "name": "general-purpose register",
        "type": "Register",
        "descriptions": [
          "Register that receives 4-bit mask from MOVMSKPS instruction for branching"
        ],
        "evidence": [],
        "source_pages": [
          260
        ]
      },
      "movhps": {
        "id": "movhps",
        "name": "MOVHPS",
        "type": "Instruction",
        "descriptions": [
          "Moves two packed single precision floats between memory/XMM high quadword; low quadword unchanged"
        ],
        "evidence": [],
        "source_pages": [
          260
        ]
      },
      "movlhps": {
        "id": "movlhps",
        "name": "MOVLHPS",
        "type": "Instruction",
        "descriptions": [
          "Moves two packed single precision floats from source XMM low to dest XMM high qword; low qword unchanged"
        ],
        "evidence": [],
        "source_pages": [
          260
        ]
      },
      "movhlps": {
        "id": "movhlps",
        "name": "MOVHLPS",
        "type": "Instruction",
        "descriptions": [
          "Moves two packed single precision floats from source XMM high to dest XMM low qword; high qword unchanged"
        ],
        "evidence": [],
        "source_pages": [
          260
        ]
      },
      "movmskps": {
        "id": "movmskps",
        "name": "MOVMSKPS",
        "type": "Instruction",
        "descriptions": [
          "Transfers MSB of four packed single precision floats in XMM to general-purpose register; 4-bit value for branching"
        ],
        "evidence": [],
        "source_pages": [
          260
        ]
      },
      "addps": {
        "id": "addps",
        "name": "ADDPS",
        "type": "Instruction",
        "descriptions": [
          "Adds two packed single precision floating-point operands"
        ],
        "evidence": [],
        "source_pages": [
          260
        ]
      },
      "addss": {
        "id": "addss",
        "name": "ADDSS",
        "type": "Instruction",
        "descriptions": [
          "Adds low single precision floating-point values of two operands; result in destination low doubleword"
        ],
        "evidence": [],
        "source_pages": [
          260
        ]
      },
      "xsave_feature_set": {
        "id": "xsave_feature_set",
        "name": "XSAVE feature set",
        "type": "Feature Set",
        "descriptions": [
          "Manages state components via XCR0 and CR4.OSXSAVE configuration"
        ],
        "evidence": [],
        "source_pages": [
          323
        ]
      },
      "xcr0": {
        "id": "xcr0",
        "name": "XCR0",
        "type": "Register",
        "descriptions": [
          "Controls management of XSAVE-enabled state components via bit settings",
          "Extended control register holding state enable bits"
        ],
        "evidence": [],
        "source_pages": [
          323,
          363
        ]
      },
      "cr4_osxsave_bit_18": {
        "id": "cr4_osxsave_bit_18",
        "name": "CR4.OSXSAVE[bit 18]",
        "type": "Register Bit",
        "descriptions": [
          "Enables XSAVE feature set when set to 1; disables if 0"
        ],
        "evidence": [],
        "source_pages": [
          323
        ]
      },
      "invalid_opcode_exception_#ud": {
        "id": "invalid_opcode_exception_#ud",
        "name": "invalid-opcode exception (#UD)",
        "type": "Exception",
        "descriptions": [
          "Triggered by executing unenabled XSAVE feature instructions"
        ],
        "evidence": [],
        "source_pages": [
          323
        ]
      },
      "cpuid_instruction": {
        "id": "cpuid_instruction",
        "name": "CPUID instruction",
        "type": "Instruction",
        "descriptions": [
          "Enumerates XSAVE support via sub-leaves (e.g., 01H, 0DH)"
        ],
        "evidence": [],
        "source_pages": [
          323
        ]
      },
      "xsave_enabled_features": {
        "id": "xsave_enabled_features",
        "name": "XSAVE-enabled features",
        "type": "Feature",
        "descriptions": [
          "Features with user state components managed by XSAVE via XCR0"
        ],
        "evidence": [],
        "source_pages": [
          323
        ]
      },
      "user_state_components": {
        "id": "user_state_components",
        "name": "User state components",
        "type": "State Component",
        "descriptions": [
          "State elements (e.g., x87, SSE) managed or not by XSAVE"
        ],
        "evidence": [],
        "source_pages": [
          323
        ]
      },
      "xsaveopt_instruction": {
        "id": "xsaveopt_instruction",
        "name": "XSAVEOPT instruction",
        "type": "Instruction",
        "descriptions": [
          "Supported if CPUID.0DH.01H.EAX[0] = 1; else causes #UD"
        ],
        "evidence": [],
        "source_pages": [
          323
        ]
      },
      "legacy_simd_isa": {
        "id": "legacy_simd_isa",
        "name": "Legacy SIMD ISA",
        "type": "ISA",
        "descriptions": [
          "Source ISA promoted to 128-bit AVX instructions"
        ],
        "evidence": [],
        "source_pages": [
          360
        ]
      },
      "128_bit_arithmetic_intel_avx_instructions": {
        "id": "128_bit_arithmetic_intel_avx_instructions",
        "name": "128-Bit Arithmetic Intel® AVX Instructions",
        "type": "ISA",
        "descriptions": [
          "Target instructions from Legacy SIMD ISA promotion"
        ],
        "evidence": [],
        "source_pages": [
          360
        ]
      },
      "vex_128_encoding": {
        "id": "vex_128_encoding",
        "name": "VEX.128 Encoding",
        "type": "VEX Encoding",
        "descriptions": [
          "Encoding supporting legacy SIMD promotion to 128-bit AVX",
          "128-bit VEX encoding for AVX instructions"
        ],
        "evidence": [],
        "source_pages": [
          360,
          362
        ]
      },
      "vex_256_encoding": {
        "id": "vex_256_encoding",
        "name": "VEX.256 Encoding",
        "type": "VEX Encoding",
        "descriptions": [
          "Encoding not supporting most legacy SIMD promotions",
          "256-bit VEX encoding for AVX instructions"
        ],
        "evidence": [],
        "source_pages": [
          360,
          362
        ]
      },
      "cpuid_01h_ecx_ssse3_9": {
        "id": "cpuid_01h_ecx_ssse3_9",
        "name": "CPUID.01H:ECX.SSSE3[9]",
        "type": "CPUID Feature",
        "descriptions": [
          "CPUID flag indicating SSSE3 feature support"
        ],
        "evidence": [],
        "source_pages": [
          360
        ]
      },
      "cpuid_01h_ecx_sse4_1_19": {
        "id": "cpuid_01h_ecx_sse4_1_19",
        "name": "CPUID.01H:ECX.SSE4_1[19]",
        "type": "CPUID Feature",
        "descriptions": [
          "CPUID flag indicating SSE4.1 feature support"
        ],
        "evidence": [],
        "source_pages": [
          360
        ]
      },
      "pmaddwd": {
        "id": "pmaddwd",
        "name": "PMADDWD",
        "type": "Instruction",
        "descriptions": [
          "Legacy SIMD instruction promoted via VEX.128"
        ],
        "evidence": [],
        "source_pages": [
          360
        ]
      },
      "pcmpeqb": {
        "id": "pcmpeqb",
        "name": "PCMPEQB",
        "type": "Instruction",
        "descriptions": [
          "Legacy SIMD instruction with VEX.128 support"
        ],
        "evidence": [],
        "source_pages": [
          360
        ]
      },
      "phsubw": {
        "id": "phsubw",
        "name": "PHSUBW",
        "type": "concept",
        "descriptions": [],
        "evidence": [],
        "source_pages": [
          360
        ]
      },
      "dppd": {
        "id": "dppd",
        "name": "DPPD",
        "type": "concept",
        "descriptions": [],
        "evidence": [],
        "source_pages": [
          360
        ]
      },
      "vi": {
        "id": "vi",
        "name": "VI",
        "type": "concept",
        "descriptions": [],
        "evidence": [],
        "source_pages": [
          360
        ]
      },
      "intel_avx": {
        "id": "intel_avx",
        "name": "Intel AVX",
        "type": "Technology",
        "descriptions": [
          "Provides VEX-encoded data processing instructions for SIMD programming",
          "Instruction set operating on 256-bit YMM register state"
        ],
        "evidence": [],
        "source_pages": [
          361,
          363
        ]
      },
      "vex_encoded_instructions": {
        "id": "vex_encoded_instructions",
        "name": "VEX-encoded instructions",
        "type": "Instruction Set",
        "descriptions": [
          "Use VEX prefix encoding; same functionality as SIMD prefix on XMM registers"
        ],
        "evidence": [],
        "source_pages": [
          361
        ]
      },
      "128_bit_vector_processing": {
        "id": "128_bit_vector_processing",
        "name": "128-bit vector processing",
        "type": "Processing Type",
        "descriptions": [
          "Handles 128-bit SIMD data with VEX-encoded non-arithmetic primitives"
        ],
        "evidence": [],
        "source_pages": [
          361
        ]
      },
      "non_unit_strided_fetching": {
        "id": "non_unit_strided_fetching",
        "name": "Non-unit-strided fetching",
        "type": "Data Fetching Capability",
        "descriptions": [
          "Enables broadcast and masked move for SIMD floating-point data"
        ],
        "evidence": [],
        "source_pages": [
          361
        ]
      },
      "intra_register_manipulation": {
        "id": "intra_register_manipulation",
        "name": "Intra-register manipulation",
        "type": "Data Manipulation Capability",
        "descriptions": [
          "Facilitates permutation of floating-point elements in 128-bit SIMD registers"
        ],
        "evidence": [],
        "source_pages": [
          361
        ]
      },
      "branch_handling": {
        "id": "branch_handling",
        "name": "Branch handling",
        "type": "Programming Capability",
        "descriptions": [
          "Provides primitives for SIMD branches using floating-point/integer data"
        ],
        "evidence": [],
        "source_pages": [
          361
        ]
      },
      "variable_blend_instructions": {
        "id": "variable_blend_instructions",
        "name": "Variable blend instructions",
        "type": "Instruction",
        "descriptions": [
          "Supports four-operand, non-destructive syntax for branch condition handling"
        ],
        "evidence": [],
        "source_pages": [
          361
        ]
      },
      "vbroadcastss": {
        "id": "vbroadcastss",
        "name": "VBROADCASTSS",
        "type": "Instruction",
        "descriptions": [
          "Broadcasts single precision element from mem to 128-bit xmm1 destination"
        ],
        "evidence": [],
        "source_pages": [
          361
        ]
      },
      "128_bit_intel_avx_instruction_enhancement": {
        "id": "128_bit_intel_avx_instruction_enhancement",
        "name": "128-bit Intel® AVX Instruction Enhancement",
        "type": "Instruction Set",
        "descriptions": [
          "Enhanced 128-bit AVX instructions including permute and test"
        ],
        "evidence": [],
        "source_pages": [
          362
        ]
      },
      "vpermilpd": {
        "id": "vpermilpd",
        "name": "VPERMILPD",
        "type": "Instruction",
        "descriptions": [
          "Permute double precision floating-point values with controls"
        ],
        "evidence": [],
        "source_pages": [
          362
        ]
      },
      "vpermilps": {
        "id": "vpermilps",
        "name": "VPERMILPS",
        "type": "Instruction",
        "descriptions": [
          "Permute single precision floating-point values with controls"
        ],
        "evidence": [],
        "source_pages": [
          362
        ]
      },
      "vtestps": {
        "id": "vtestps",
        "name": "VTESTPS",
        "type": "Instruction",
        "descriptions": [
          "Set ZF/CF based on packed single precision sign bits"
        ],
        "evidence": [],
        "source_pages": [
          362
        ]
      },
      "vtestpd": {
        "id": "vtestpd",
        "name": "VTESTPD",
        "type": "Instruction",
        "descriptions": [
          "Set ZF/CF based on packed double precision sign bits"
        ],
        "evidence": [],
        "source_pages": [
          362
        ]
      },
      "legacy_simd_non_arithmetic_isa": {
        "id": "legacy_simd_non_arithmetic_isa",
        "name": "Legacy SIMD non-arithmetic ISA",
        "type": "ISA Component",
        "descriptions": [
          "Legacy SIMD instructions without arithmetic operations"
        ],
        "evidence": [],
        "source_pages": [
          362
        ]
      },
      "table_14_7": {
        "id": "table_14_7",
        "name": "Table 14-7",
        "type": "concept",
        "descriptions": [],
        "evidence": [],
        "source_pages": [
          362
        ]
      },
      "ymm_register_state": {
        "id": "ymm_register_state",
        "name": "YMM register state",
        "type": "Register State",
        "descriptions": [
          "256-bit register state used by Intel AVX instructions"
        ],
        "evidence": [],
        "source_pages": [
          363
        ]
      },
      "cpuid_01h_ecx_osxsave": {
        "id": "cpuid_01h_ecx_osxsave",
        "name": "CPUID.01H:ECX.OSXSAVE",
        "type": "Feature Flag",
        "descriptions": [
          "CPUID flag indicating OS support for XGETBV"
        ],
        "evidence": [],
        "source_pages": [
          363
        ]
      },
      "xgetbv": {
        "id": "xgetbv",
        "name": "XGETBV",
        "type": "Instruction",
        "descriptions": [
          "Instruction to check enabled state in XCR0",
          "Instruction to retrieve XCR0 register value"
        ],
        "evidence": [],
        "source_pages": [
          363,
          364
        ]
      },
      "cpuid_01h_ecx_avx": {
        "id": "cpuid_01h_ecx_avx",
        "name": "CPUID.01H:ECX.AVX",
        "type": "Feature Flag",
        "descriptions": [
          "CPUID flag indicating AVX instruction support"
        ],
        "evidence": [],
        "source_pages": [
          363
        ]
      },
      "xsave": {
        "id": "xsave",
        "name": "XSAVE",
        "type": "Instruction",
        "descriptions": [
          "Instruction for saving processor extended state"
        ],
        "evidence": [],
        "source_pages": [
          363
        ]
      },
      "xrstor": {
        "id": "xrstor",
        "name": "XRSTOR",
        "type": "Instruction",
        "descriptions": [
          "Instruction for restoring processor extended state"
        ],
        "evidence": [],
        "source_pages": [
          363
        ]
      },
      "supports_avx": {
        "id": "supports_avx",
        "name": "supports_AVX()",
        "type": "Function",
        "descriptions": [
          "Function to detect Intel AVX instruction support"
        ],
        "evidence": [],
        "source_pages": [
          364
        ]
      },
      "cpuid_01h_ecx_avx_28": {
        "id": "cpuid_01h_ecx_avx_28",
        "name": "CPUID.01H:ECX.AVX[28]",
        "type": "CPUID Feature Flag",
        "descriptions": [
          "Hardware support indicator for Intel AVX"
        ],
        "evidence": [],
        "source_pages": [
          364
        ]
      },
      "cpuid_01h_ecx_xsave_26": {
        "id": "cpuid_01h_ecx_xsave_26",
        "name": "CPUID.01H:ECX.XSAVE[26]",
        "type": "CPUID Feature Flag",
        "descriptions": [
          "Hardware support indicator for XSAVE"
        ],
        "evidence": [],
        "source_pages": [
          364
        ]
      },
      "osxsave_feature_flag": {
        "id": "osxsave_feature_flag",
        "name": "OSXSAVE feature flag",
        "type": "Feature Flag",
        "descriptions": [
          "Indicates OS support for XSAVE functionality"
        ],
        "evidence": [],
        "source_pages": [
          364
        ]
      },
      "avx_feature_flag": {
        "id": "avx_feature_flag",
        "name": "AVX feature flag",
        "type": "Feature Flag",
        "descriptions": [
          "Indicates hardware support for AVX instructions"
        ],
        "evidence": [],
        "source_pages": [
          364
        ]
      },
      "xcr0_register": {
        "id": "xcr0_register",
        "name": "XCR0 register",
        "type": "Register",
        "descriptions": [
          "Stores state management enablement status",
          "Queried via XGETBV to check XMM/YMM state support"
        ],
        "evidence": [],
        "source_pages": [
          364,
          365
        ]
      },
      "ymm_state": {
        "id": "ymm_state",
        "name": "YMM state",
        "type": "CPU State",
        "descriptions": [
          "SIMD state used by Intel AVX instructions"
        ],
        "evidence": [],
        "source_pages": [
          364
        ]
      },
      "vaesdec_instruction": {
        "id": "vaesdec_instruction",
        "name": "VAESDEC instruction",
        "type": "Instruction",
        "descriptions": [
          "Operates on YMM states; part of VEX-encoded AES-NI instructions"
        ],
        "evidence": [],
        "source_pages": [
          365
        ]
      },
      "vaesenclast_instruction": {
        "id": "vaesenclast_instruction",
        "name": "VAESENCLAST instruction",
        "type": "Instruction",
        "descriptions": [
          "Operates on YMM states; part of VEX-encoded AES-NI instructions"
        ],
        "evidence": [],
        "source_pages": [
          365
        ]
      },
      "vpclmulqdq_instruction": {
        "id": "vpclmulqdq_instruction",
        "name": "VPCLMULQDQ instruction",
        "type": "Instruction",
        "descriptions": [
          "VEX-encoded instruction requiring PCLMULQDQ flag and AVX support"
        ],
        "evidence": [],
        "source_pages": [
          365
        ]
      },
      "cpuid_01h_ecx_aes_25_flag": {
        "id": "cpuid_01h_ecx_aes_25_flag",
        "name": "CPUID.01H:ECX.AES[25] flag",
        "type": "CPUID Flag",
        "descriptions": [
          "Prerequisite flag for VEX-encoded AES-NI instruction detection"
        ],
        "evidence": [],
        "source_pages": [
          365
        ]
      },
      "cpuid_01h_ecx_pclmulqdq_1_flag": {
        "id": "cpuid_01h_ecx_pclmulqdq_1_flag",
        "name": "CPUID.01H:ECX.PCLMULQDQ[1] flag",
        "type": "CPUID Flag",
        "descriptions": [
          "Prerequisite flag for VPCLMULQDQ instruction detection"
        ],
        "evidence": [],
        "source_pages": [
          365
        ]
      },
      "xgetbv_instruction": {
        "id": "xgetbv_instruction",
        "name": "XGETBV instruction",
        "type": "Instruction",
        "descriptions": [
          "Retrieves XCR0 value to check OS-enabled XMM/YMM support"
        ],
        "evidence": [],
        "source_pages": [
          365
        ]
      },
      "vex_encoded_aes_ni_detection_sequence": {
        "id": "vex_encoded_aes_ni_detection_sequence",
        "name": "VEX-encoded AES-NI detection sequence",
        "type": "Detection Sequence",
        "descriptions": [
          "Combines AES flag check and Intel AVX application support check"
        ],
        "evidence": [],
        "source_pages": [
          365
        ]
      },
      "intel_avx_application_support": {
        "id": "intel_avx_application_support",
        "name": "Intel AVX application support",
        "type": "concept",
        "descriptions": [],
        "evidence": [],
        "source_pages": [
          365
        ]
      },
      "vpclmulqdq_detection_sequence": {
        "id": "vpclmulqdq_detection_sequence",
        "name": "VPCLMULQDQ detection sequence",
        "type": "concept",
        "descriptions": [],
        "evidence": [],
        "source_pages": [
          365
        ]
      },
      "xmm_ymm_state_support": {
        "id": "xmm_ymm_state_support",
        "name": "XMM/YMM state support",
        "type": "concept",
        "descriptions": [],
        "evidence": [],
        "source_pages": [
          365
        ]
      }
    },
    "relationships": [
      {
        "source": "intel_streaming_simd_extensions_intel_sse",
        "target": "ia_32_processors",
        "type": "compatible with",
        "description": "Intel SSE is fully compatible with software written for IA-32 processors, allowing unmodified execution.",
        "evidence_quote": "Intel SSE is fully compatible with all software written for IA-32 processors. All existing software continues to run correctly, without modification, on processors that incorporate Intel SSE.",
        "source_page": 254
      },
      {
        "source": "intel_streaming_simd_extensions_intel_sse",
        "target": "ia_32_execution_modes",
        "type": "accessible from",
        "description": "Intel SSE can be accessed from all IA-32 execution modes.",
        "evidence_quote": "Intel SSE is accessible from all IA-32 execution modes: protected mode, real address mode, and virtual-8086 mode.",
        "source_page": 254
      },
      {
        "source": "intel_sse_programming_environment",
        "target": "xmm_registers",
        "type": "includes",
        "description": "The Intel SSE programming environment includes XMM registers as a component.",
        "evidence_quote": "the programming environment for Intel SSE, including: XMM registers, the packed single precision floating-point data type, and Intel SSE instructions.",
        "source_page": 254
      },
      {
        "source": "intel_sse_programming_environment",
        "target": "mxcsr_register",
        "type": "includes",
        "description": "The Intel SSE programming environment includes the MXCSR register as a component.",
        "evidence_quote": "Figure 10-1 shows the execution environment for Intel SSE. All Intel SSE instructions operate on the XMM registers, MMX registers, and/or memory as follows: ... MXCSR register...",
        "source_page": 254
      },
      {
        "source": "intel_sse_programming_environment",
        "target": "mmx_registers",
        "type": "includes",
        "description": "The Intel SSE programming environment includes MMX registers as a component.",
        "evidence_quote": "Figure 10-1 shows the execution environment for Intel SSE. All Intel SSE instructions operate on the XMM registers, MMX registers, and/or memory as follows: ... MMX registers...",
        "source_page": 254
      },
      {
        "source": "intel_sse_programming_environment",
        "target": "general_purpose_registers",
        "type": "includes",
        "description": "The Intel SSE programming environment includes general-purpose registers as a component.",
        "evidence_quote": "Figure 10-1 shows the execution environment for Intel SSE. All Intel SSE instructions operate on the XMM registers, MMX registers, and/or memory as follows: ... General-purpose registers...",
        "source_page": 254
      },
      {
        "source": "intel_sse_programming_environment",
        "target": "packed_single_precision_floating_point_data_type",
        "type": "includes",
        "description": "The Intel SSE programming environment includes the packed single precision floating-point data type.",
        "evidence_quote": "the programming environment for Intel SSE, including: XMM registers, the packed single precision floating-point data type, and Intel SSE instructions.",
        "source_page": 254
      },
      {
        "source": "intel_sse_programming_environment",
        "target": "intel_sse_instructions",
        "type": "includes",
        "description": "The Intel SSE programming environment includes Intel SSE instructions.",
        "evidence_quote": "the programming environment for Intel SSE, including: XMM registers, the packed single precision floating-point data type, and Intel SSE instructions.",
        "source_page": 254
      },
      {
        "source": "xmm_registers",
        "target": "packed_single_precision_floating_point_data_type",
        "type": "operates on",
        "description": "XMM registers are used to operate on packed or scalar single precision floating-point data.",
        "evidence_quote": "XMM registers — These eight registers... are used to operate on packed or scalar single precision floating-point data.",
        "source_page": 254
      },
      {
        "source": "mmx_registers",
        "target": "64_bit_packed_integer_data",
        "type": "operates on",
        "description": "MMX registers are used to perform operations on 64-bit packed integer data.",
        "evidence_quote": "MMX registers — These eight registers... are used to perform operations on 64-bit packed integer data.",
        "source_page": 254
      },
      {
        "source": "mmx_registers",
        "target": "xmm_registers",
        "type": "interoperates with",
        "description": "MMX registers hold operands for some operations between MMX and XMM registers.",
        "evidence_quote": "They are also used to hold operands for some operations performed between the MMX and XMM registers.",
        "source_page": 254
      },
      {
        "source": "mxcsr_register",
        "target": "simd_floating_point_operations",
        "type": "controls",
        "description": "The MXCSR register provides status and control bits used in SIMD floating-point operations.",
        "evidence_quote": "MXCSR register — This 32-bit register... provides status and control bits used in SIMD floating-point operations.",
        "source_page": 254
      },
      {
        "source": "general_purpose_registers",
        "target": "ia_32_addressing_modes",
        "type": "used with",
        "description": "General-purpose registers are used along with IA-32 addressing modes to address memory operands.",
        "evidence_quote": "General-purpose registers — The eight general-purpose registers... are used along with the existing IA-32 addressing modes to address operands in memory.",
        "source_page": 254
      },
      {
        "source": "general_purpose_registers",
        "target": "memory_operands",
        "type": "addresses",
        "description": "General-purpose registers address operands in memory using IA-32 addressing modes.",
        "evidence_quote": "General-purpose registers — The eight general-purpose registers... are used along with the existing IA-32 addressing modes to address operands in memory.",
        "source_page": 254
      },
      {
        "source": "general_purpose_registers",
        "target": "intel_sse_instructions",
        "type": "holds operands for",
        "description": "General-purpose registers are used to hold operands for some Intel SSE instructions",
        "evidence_quote": "The general-purpose registers are also used to hold operands for some SSE instructions",
        "source_page": 255
      },
      {
        "source": "general_purpose_registers",
        "target": "memory_addressing",
        "type": "used for",
        "description": "General-purpose registers are used to address memory",
        "evidence_quote": "XMM registers can only be used to perform calculations on data; they cannot be used to address memory. Addressing memory is accomplished by using the general-purpose registers.",
        "source_page": 255
      },
      {
        "source": "eflags_register",
        "target": "compare_operations",
        "type": "records result of",
        "description": "EFLAGS register is used to record result of some compare operations",
        "evidence_quote": "EFLAGS register — This 32-bit register (see Figure 3-7) is used to record result of some compare operations.",
        "source_page": 255
      },
      {
        "source": "64_bit_mode",
        "target": "xmm_registers",
        "type": "adds additional",
        "description": "64-bit mode provides eight additional XMM registers (XMM8-XMM15)",
        "evidence_quote": "In 64-bit mode, eight additional XMM registers are accessible. Registers XMM8-XMM15 are accessed by using REX prefixes.",
        "source_page": 255
      },
      {
        "source": "compatibility_mode",
        "target": "protected_mode",
        "type": "functions like",
        "description": "In compatibility mode, Intel SSE functions like it does in protected mode",
        "evidence_quote": "In compatibility mode, Intel SSE functions like it does in protected mode.",
        "source_page": 255
      },
      {
        "source": "intel_sse_instructions",
        "target": "xmm_registers",
        "type": "uses",
        "description": "Intel SSE instructions use the XMM registers to operate on packed single precision floating-point operands",
        "evidence_quote": "Intel SSE instructions use the XMM registers only to operate on packed single precision floating-point operands.",
        "source_page": 255
      },
      {
        "source": "sse2_extensions",
        "target": "xmm_registers",
        "type": "expands functions of",
        "description": "SSE2 extensions expand the functions of the XMM registers to handle double precision floating-point and packed integer operands",
        "evidence_quote": "SSE2 extensions expand the functions of the XMM registers to operand on packed or scalar double precision floating-point operands and packed integer operands",
        "source_page": 255
      },
      {
        "source": "xmm_registers",
        "target": "memory_addressing",
        "type": "cannot be used for",
        "description": "XMM registers cannot be used to address memory",
        "evidence_quote": "XMM registers can only be used to perform calculations on data; they cannot be used to address memory.",
        "source_page": 255
      },
      {
        "source": "rex_prefixes",
        "target": "xmm8_xmm15",
        "type": "accesses",
        "description": "REX prefixes are used to access XMM8-XMM15 registers in 64-bit mode",
        "evidence_quote": "Registers XMM8-XMM15 are accessed by using REX prefixes.",
        "source_page": 255
      },
      {
        "source": "rex_prefixes",
        "target": "64_bit_general_purpose_registers",
        "type": "accesses",
        "description": "REX.W prefix is used to access 64-bit general-purpose registers",
        "evidence_quote": "Use the REX.W prefix to access 64-bit general-purpose registers.",
        "source_page": 255
      },
      {
        "source": "mxcsr_control_and_status_register",
        "target": "intel_sse",
        "type": "controls and monitors",
        "description": "MXCSR register contains control and status information for Intel SSE SIMD floating-point operations",
        "evidence_quote": "The 32-bit MXCSR register ... contains control and status information for Intel SSE, SSE2, and SSE3 SIMD floating-point operations.",
        "source_page": 255
      },
      {
        "source": "mxcsr_control_and_status_register",
        "target": "sse2",
        "type": "controls and monitors",
        "description": "MXCSR register contains control and status information for SSE2 SIMD floating-point operations",
        "evidence_quote": "The 32-bit MXCSR register ... contains control and status information for Intel SSE, SSE2, and SSE3 SIMD floating-point operations.",
        "source_page": 255
      },
      {
        "source": "mxcsr_control_and_status_register",
        "target": "sse3",
        "type": "controls and monitors",
        "description": "MXCSR register contains control and status information for SSE3 SIMD floating-point operations",
        "evidence_quote": "The 32-bit MXCSR register ... contains control and status information for Intel SSE, SSE2, and SSE3 SIMD floating-point operations.",
        "source_page": 255
      },
      {
        "source": "intel_sse_instructions",
        "target": "general_purpose_registers",
        "type": "operates on",
        "description": "Some Intel SSE instructions may be used to operate on general-purpose registers",
        "evidence_quote": "Some Intel SSE instructions may be used to operate on general-purpose registers.",
        "source_page": 255
      },
      {
        "source": "mxcsr_register",
        "target": "flush_to_zero_flag",
        "type": "has component",
        "description": "Contains bit 15 (FTZ) enabling flush-to-zero mode",
        "evidence_quote": "",
        "source_page": 256
      },
      {
        "source": "mxcsr_register",
        "target": "denormals_are_zeros_flag",
        "type": "has component",
        "description": "Controls handling of denormal source operands",
        "evidence_quote": "",
        "source_page": 256
      },
      {
        "source": "ldmxcsr_instruction",
        "target": "mxcsr_register",
        "type": "loads",
        "description": "Loads MXCSR contents from memory",
        "evidence_quote": "",
        "source_page": 256
      },
      {
        "source": "fxrstor_instruction",
        "target": "mxcsr_register",
        "type": "loads",
        "description": "Loads MXCSR contents from memory",
        "evidence_quote": "",
        "source_page": 256
      },
      {
        "source": "stmxcsr_instruction",
        "target": "mxcsr_register",
        "type": "stores",
        "description": "Stores MXCSR contents to memory",
        "evidence_quote": "",
        "source_page": 256
      },
      {
        "source": "fxsave_instruction",
        "target": "mxcsr_register",
        "type": "stores",
        "description": "Stores MXCSR contents to memory",
        "evidence_quote": "",
        "source_page": 256
      },
      {
        "source": "mxcsr_register",
        "target": "simd_floating_point_exceptions",
        "type": "contains",
        "description": "Bits 0-5 indicate detected exceptions (sticky flags)",
        "evidence_quote": "",
        "source_page": 256
      },
      {
        "source": "fxrstor_instruction",
        "target": "general_protection_exception_#gp",
        "type": "causes",
        "description": "Writing non-zero reserved bits (16-31) triggers #GP",
        "evidence_quote": "",
        "source_page": 256
      },
      {
        "source": "flush_to_zero_mode",
        "target": "ieee_standard_754",
        "type": "Incompatibility",
        "description": "flush-to-zero mode is not compatible with IEEE Standard 754",
        "evidence_quote": "",
        "source_page": 257
      },
      {
        "source": "denormals_are_zeros_mode_daz",
        "target": "ieee_standard_754",
        "type": "Incompatibility",
        "description": "denormals-are-zeros mode is not compatible with IEEE Standard 754",
        "evidence_quote": "",
        "source_page": 257
      },
      {
        "source": "mxcsr_register",
        "target": "denormals_are_zeros_mode_daz",
        "type": "Enables",
        "description": "Bit 6 of MXCSR register enables denormals-are-zeros mode",
        "evidence_quote": "",
        "source_page": 257
      },
      {
        "source": "xmm_registers",
        "target": "sse_sse2_sse3",
        "type": "Shared State",
        "description": "XMM registers are shared state between SSE, SSE2, and SSE3",
        "evidence_quote": "",
        "source_page": 257
      },
      {
        "source": "fxsave_instruction",
        "target": "xmm_registers",
        "type": "Saves",
        "description": "FXSAVE instruction saves XMM registers as part of SSE state",
        "evidence_quote": "",
        "source_page": 257
      },
      {
        "source": "fxrstor_instruction",
        "target": "xmm_registers",
        "type": "Restores",
        "description": "FXRSTOR instruction restores XMM registers as part of SSE state",
        "evidence_quote": "",
        "source_page": 257
      },
      {
        "source": "xmm_registers",
        "target": "x87_fpu_mmx_registers",
        "type": "Independence",
        "description": "XMM registers independent of x87 FPU and MMX; parallel operation possible",
        "evidence_quote": "",
        "source_page": 257
      },
      {
        "source": "128_bit_packed_single_precision_floating_point_data_type",
        "target": "xmm_registers",
        "type": "Operated In",
        "description": "128-bit packed single precision data type is operated on in XMM registers",
        "evidence_quote": "",
        "source_page": 258
      },
      {
        "source": "xmm_registers",
        "target": "mmx_registers",
        "type": "Conversion With",
        "description": "Intel SSE provides conversion instructions between XMM and MMX registers",
        "evidence_quote": "",
        "source_page": 258
      },
      {
        "source": "intel_sse_instruction_set",
        "target": "packed_and_scalar_single_precision_floating_point_instructions",
        "type": "Includes Subgroup",
        "description": "Intel SSE instruction set includes packed and scalar single precision FP instructions subgroup",
        "evidence_quote": "",
        "source_page": 258
      },
      {
        "source": "packed_and_scalar_single_precision_floating_point_instructions",
        "target": "data_movement_instructions",
        "type": "Includes Subtype",
        "description": "Packed/scalar FP instructions include data movement instructions",
        "evidence_quote": "",
        "source_page": 258
      },
      {
        "source": "packed_and_scalar_single_precision_floating_point_instructions",
        "target": "arithmetic_instructions",
        "type": "Includes Subtype",
        "description": "Packed/scalar FP instructions include arithmetic instructions",
        "evidence_quote": "",
        "source_page": 258
      },
      {
        "source": "128_bit_packed_single_precision_floating_point_data_type",
        "target": "movups_instruction",
        "type": "Supported By",
        "description": "MOVUPS instruction supports unaligned accesses for 128-bit packed memory operands",
        "evidence_quote": "",
        "source_page": 258
      },
      {
        "source": "intel_sse_instruction_set",
        "target": "64_bit_simd_integer_instructions",
        "type": "Includes Functional Group",
        "description": "Intel SSE instruction set includes 64-bit SIMD integer instructions group",
        "evidence_quote": "",
        "source_page": 258
      },
      {
        "source": "packed_and_scalar_single_precision_floating_point_instructions",
        "target": "conversion_instructions",
        "type": "Includes Subtype",
        "description": "Packed/scalar FP instructions include conversion instructions",
        "evidence_quote": "",
        "source_page": 258
      },
      {
        "source": "movaps_instruction",
        "target": "xmm_registers",
        "type": "Transfers Data Between",
        "description": "Transfers data between XMM registers and memory",
        "evidence_quote": "",
        "source_page": 259
      },
      {
        "source": "movaps_instruction",
        "target": "general_protection_exception_#gp",
        "type": "Generates",
        "description": "Generates #GP if memory address not 16-byte aligned",
        "evidence_quote": "",
        "source_page": 259
      },
      {
        "source": "movups_instruction",
        "target": "xmm_registers",
        "type": "Transfers Data Between",
        "description": "Transfers data between XMM registers and memory",
        "evidence_quote": "",
        "source_page": 259
      },
      {
        "source": "movss_instruction",
        "target": "xmm_registers",
        "type": "Transfers Data Between",
        "description": "Transfers scalar value between XMM registers and memory",
        "evidence_quote": "",
        "source_page": 259
      },
      {
        "source": "movlps_instruction",
        "target": "xmm_registers",
        "type": "Moves Data To",
        "description": "Moves two values to low quadword; high quadword unchanged",
        "evidence_quote": "",
        "source_page": 259
      },
      {
        "source": "scalar_single_precision_floating_point_instructions",
        "target": "x0_y0",
        "type": "Operates On",
        "description": "Operate on low doublewords (X0, Y0) of source operands",
        "evidence_quote": "",
        "source_page": 259
      },
      {
        "source": "packed_single_precision_floating_point_operations",
        "target": "x3_y3_x2_y2_x1_y1_x0_y0",
        "type": "Performs OP On",
        "description": "Perform OP on specified doublewords of source operands",
        "evidence_quote": "",
        "source_page": 259
      },
      {
        "source": "intel_sse_data_movement_instructions",
        "target": "movaps_instruction",
        "type": "Includes",
        "description": "Includes MOVAPS, MOVUPS, MOVSS, MOVLPS instructions",
        "evidence_quote": "",
        "source_page": 259
      },
      {
        "source": "movhps",
        "target": "xmm_register",
        "type": "Uses",
        "description": "Moves data to/from high quadword of XMM register",
        "evidence_quote": "",
        "source_page": 260
      },
      {
        "source": "movlhps",
        "target": "xmm_register",
        "type": "Uses",
        "description": "Moves data between source and destination XMM registers",
        "evidence_quote": "",
        "source_page": 260
      },
      {
        "source": "movhlps",
        "target": "xmm_register",
        "type": "Uses",
        "description": "Moves data between source and destination XMM registers",
        "evidence_quote": "",
        "source_page": 260
      },
      {
        "source": "movmskps",
        "target": "xmm_register",
        "type": "Uses",
        "description": "Takes input from XMM register containing packed floats",
        "evidence_quote": "",
        "source_page": 260
      },
      {
        "source": "movmskps",
        "target": "general_purpose_register",
        "type": "Outputs to",
        "description": "Transfers 4-bit mask to general-purpose register",
        "evidence_quote": "",
        "source_page": 260
      },
      {
        "source": "addps",
        "target": "xmm_register",
        "type": "Uses",
        "description": "Operates on packed floats stored in XMM registers",
        "evidence_quote": "",
        "source_page": 260
      },
      {
        "source": "addss",
        "target": "xmm_register",
        "type": "Uses",
        "description": "Operates on scalar float in XMM register low doubleword",
        "evidence_quote": "",
        "source_page": 260
      },
      {
        "source": "addps",
        "target": "addss",
        "type": "Variant of",
        "description": "Packed version; ADDSS is scalar variant",
        "evidence_quote": "",
        "source_page": 260
      },
      {
        "source": "xsave_feature_set",
        "target": "cr4_osxsave_bit_18",
        "type": "Prerequisite",
        "description": "Enabled only if CR4.OSXSAVE[bit 18] is set to 1",
        "evidence_quote": "",
        "source_page": 323
      },
      {
        "source": "xcr0",
        "target": "xsave_enabled_features",
        "type": "Controls",
        "description": "Bit settings determine management of their state components",
        "evidence_quote": "",
        "source_page": 323
      },
      {
        "source": "xsave_enabled_features",
        "target": "invalid_opcode_exception_#ud",
        "type": "Causes",
        "description": "Executing unenabled instructions triggers #UD",
        "evidence_quote": "",
        "source_page": 323
      },
      {
        "source": "cpuid_instruction",
        "target": "xsave_feature_set",
        "type": "Enumerates",
        "description": "Reports support via CPUID.01H:ECX.XSAVE[26] bit",
        "evidence_quote": "",
        "source_page": 323
      },
      {
        "source": "cpuid_instruction",
        "target": "xsaveopt_instruction",
        "type": "Enumerates",
        "description": "Support indicated by CPUID.0DH.01H.EAX[0] bit",
        "evidence_quote": "",
        "source_page": 323
      },
      {
        "source": "cr4_osxsave_bit_18",
        "target": "xcr0",
        "type": "Affects",
        "description": "If 0, treats all XCR0 bits as clear for state management",
        "evidence_quote": "",
        "source_page": 323
      },
      {
        "source": "xsave_feature_set",
        "target": "user_state_components",
        "type": "Manages",
        "description": "Controls modification based on XCR0 and CR4.OSXSAVE settings",
        "evidence_quote": "",
        "source_page": 323
      },
      {
        "source": "xsave_enabled_features",
        "target": "xcr0",
        "type": "Requires",
        "description": "Need XCR0 configuration to manage their state components",
        "evidence_quote": "",
        "source_page": 323
      },
      {
        "source": "legacy_simd_isa",
        "target": "128_bit_arithmetic_intel_avx_instructions",
        "type": "is promoted to",
        "description": "Legacy SIMD ISA is promoted to 128-bit AVX instructions",
        "evidence_quote": "",
        "source_page": 360
      },
      {
        "source": "legacy_simd_isa",
        "target": "vex_128_encoding",
        "type": "uses",
        "description": "Legacy SIMD ISA uses VEX.128 Encoding for promotion",
        "evidence_quote": "",
        "source_page": 360
      },
      {
        "source": "pmaddwd",
        "target": "vex_128_encoding",
        "type": "supported by",
        "description": "PMADDWD instruction is supported by VEX.128 Encoding",
        "evidence_quote": "",
        "source_page": 360
      },
      {
        "source": "pmaddwd",
        "target": "vex_256_encoding",
        "type": "not supported by",
        "description": "PMADDWD instruction is not supported by VEX.256 Encoding",
        "evidence_quote": "",
        "source_page": 360
      },
      {
        "source": "cpuid_01h_ecx_ssse3_9",
        "target": "phsubw",
        "type": "enables",
        "description": "CPUID flag enables PHSUBW instruction promotion",
        "evidence_quote": "",
        "source_page": 360
      },
      {
        "source": "cpuid_01h_ecx_sse4_1_19",
        "target": "dppd",
        "type": "enables",
        "description": "CPUID flag enables DPPD instruction promotion",
        "evidence_quote": "",
        "source_page": 360
      },
      {
        "source": "pcmpeqb",
        "target": "vex_128_encoding",
        "type": "supported by",
        "description": "PCMPEQB instruction is supported by VEX.128 Encoding",
        "evidence_quote": "",
        "source_page": 360
      },
      {
        "source": "pmaddwd",
        "target": "vi",
        "type": "has reason not promoted",
        "description": "PMADDWD has reason 'VI' for not being promoted to VEX.256",
        "evidence_quote": "",
        "source_page": 360
      },
      {
        "source": "intel_avx",
        "target": "vex_encoded_instructions",
        "type": "includes",
        "description": "employs VEX prefix encoding for data processing",
        "evidence_quote": "",
        "source_page": 361
      },
      {
        "source": "intel_avx",
        "target": "128_bit_vector_processing",
        "type": "supports",
        "description": "via non-arithmetic primitives with VEX.128 encoding",
        "evidence_quote": "",
        "source_page": 361
      },
      {
        "source": "128_bit_vector_processing",
        "target": "non_unit_strided_fetching",
        "type": "enables",
        "description": "via broadcast and masked move SIMD data fetching primitives",
        "evidence_quote": "",
        "source_page": 361
      },
      {
        "source": "128_bit_vector_processing",
        "target": "intra_register_manipulation",
        "type": "enables",
        "description": "via permute primitives for 128-bit SIMD register data",
        "evidence_quote": "",
        "source_page": 361
      },
      {
        "source": "128_bit_vector_processing",
        "target": "branch_handling",
        "type": "includes",
        "description": "to handle branches in SIMD programming with AVX primitives",
        "evidence_quote": "",
        "source_page": 361
      },
      {
        "source": "branch_handling",
        "target": "variable_blend_instructions",
        "type": "employs",
        "description": "four-operand syntax with non-destructive source for branch conditions",
        "evidence_quote": "",
        "source_page": 361
      },
      {
        "source": "non_unit_strided_fetching",
        "target": "vbroadcastss",
        "type": "includes",
        "description": "broadcasts single element into 128-bit destination register",
        "evidence_quote": "",
        "source_page": 361
      },
      {
        "source": "vex_encoded_instructions",
        "target": "variable_blend_instructions",
        "type": "enhances",
        "description": "more flexible than SSE4's implied XMM0 mask syntax",
        "evidence_quote": "",
        "source_page": 361
      },
      {
        "source": "128_bit_intel_avx_instruction_enhancement",
        "target": "vpermilpd",
        "type": "Includes",
        "description": "Includes permute double precision floating-point instruction",
        "evidence_quote": "",
        "source_page": 362
      },
      {
        "source": "128_bit_intel_avx_instruction_enhancement",
        "target": "vpermilps",
        "type": "Includes",
        "description": "Includes permute single precision floating-point instruction",
        "evidence_quote": "",
        "source_page": 362
      },
      {
        "source": "128_bit_intel_avx_instruction_enhancement",
        "target": "vtestps",
        "type": "Includes",
        "description": "Includes test for packed single precision sign bits",
        "evidence_quote": "",
        "source_page": 362
      },
      {
        "source": "128_bit_intel_avx_instruction_enhancement",
        "target": "vtestpd",
        "type": "Includes",
        "description": "Includes test for packed double precision sign bits",
        "evidence_quote": "",
        "source_page": 362
      },
      {
        "source": "legacy_simd_non_arithmetic_isa",
        "target": "vex_256_encoding",
        "type": "Promoted To",
        "description": "Promoted to VEX-256 encoding (some instructions)",
        "evidence_quote": "",
        "source_page": 362
      },
      {
        "source": "legacy_simd_non_arithmetic_isa",
        "target": "vex_128_encoding",
        "type": "Supports",
        "description": "Supports VEX-128 encoding (promoted instructions)",
        "evidence_quote": "",
        "source_page": 362
      },
      {
        "source": "128_bit_intel_avx_instruction_enhancement",
        "target": "legacy_simd_non_arithmetic_isa",
        "type": "Includes Promoted",
        "description": "Includes promoted legacy SIMD non-arithmetic ISA",
        "evidence_quote": "",
        "source_page": 362
      },
      {
        "source": "legacy_simd_non_arithmetic_isa",
        "target": "table_14_7",
        "type": "Promotion State Listed In",
        "description": "Promotion state to VEX-128 encoding listed in Table 14-7",
        "evidence_quote": "",
        "source_page": 362
      },
      {
        "source": "intel_avx",
        "target": "ymm_register_state",
        "type": "Operates On",
        "description": "AVX instructions operate on 256-bit YMM register state",
        "evidence_quote": "",
        "source_page": 363
      },
      {
        "source": "cpuid_01h_ecx_osxsave",
        "target": "xgetbv",
        "type": "Implies Support",
        "description": "OSXSAVE=1 implies processor supports XGETBV",
        "evidence_quote": "",
        "source_page": 363
      },
      {
        "source": "cpuid_01h_ecx_osxsave",
        "target": "xsave",
        "type": "Implies Support",
        "description": "OSXSAVE=1 implies processor supports XSAVE",
        "evidence_quote": "",
        "source_page": 363
      },
      {
        "source": "cpuid_01h_ecx_osxsave",
        "target": "xrstor",
        "type": "Implies Support",
        "description": "OSXSAVE=1 implies processor supports XRSTOR",
        "evidence_quote": "",
        "source_page": 363
      },
      {
        "source": "xgetbv",
        "target": "xcr0",
        "type": "Checks",
        "description": "XGETBV verifies XCR0[2:1] = '11b' for state enable",
        "evidence_quote": "",
        "source_page": 363
      },
      {
        "source": "xcr0",
        "target": "ymm_register_state",
        "type": "Enables",
        "description": "XCR0[2:1] = '11b' enables YMM register state",
        "evidence_quote": "",
        "source_page": 363
      },
      {
        "source": "cpuid_01h_ecx_avx",
        "target": "intel_avx",
        "type": "Indicates Support",
        "description": "AVX flag indicates support for Intel AVX instructions",
        "evidence_quote": "",
        "source_page": 363
      },
      {
        "source": "intel_avx",
        "target": "cpuid_01h_ecx_osxsave",
        "type": "Prerequisite",
        "description": "AVX use requires checking OSXSAVE feature flag",
        "evidence_quote": "",
        "source_page": 363
      },
      {
        "source": "supports_avx",
        "target": "osxsave_feature_flag",
        "type": "checks",
        "description": "Checks via CPUID to verify OS support",
        "evidence_quote": "",
        "source_page": 364
      },
      {
        "source": "supports_avx",
        "target": "avx_feature_flag",
        "type": "checks",
        "description": "Checks via CPUID to verify hardware support",
        "evidence_quote": "",
        "source_page": 364
      },
      {
        "source": "supports_avx",
        "target": "xgetbv",
        "type": "uses instruction",
        "description": "Uses to retrieve XCR0 register value",
        "evidence_quote": "",
        "source_page": 364
      },
      {
        "source": "xgetbv",
        "target": "xcr0_register",
        "type": "retrieves",
        "description": "Instruction retrieves value of XCR0 register",
        "evidence_quote": "",
        "source_page": 364
      },
      {
        "source": "supports_avx",
        "target": "ymm_state",
        "type": "checks support for",
        "description": "Verifies OS enablement of YMM state",
        "evidence_quote": "",
        "source_page": 364
      },
      {
        "source": "cpuid_01h_ecx_avx_28",
        "target": "avx_feature_flag",
        "type": "insufficient indicator for",
        "description": "Hardware flag alone doesn't confirm AVX support",
        "evidence_quote": "",
        "source_page": 364
      },
      {
        "source": "cpuid_01h_ecx_xsave_26",
        "target": "osxsave_feature_flag",
        "type": "does not guarantee",
        "description": "Hardware flag doesn't ensure OS XSAVE usage",
        "evidence_quote": "",
        "source_page": 364
      },
      {
        "source": "ymm_state",
        "target": "supports_avx",
        "type": "required for",
        "description": "OS-enabled YMM state required for AVX support",
        "evidence_quote": "",
        "source_page": 364
      },
      {
        "source": "vaesdec_instruction",
        "target": "vex_encoded_aes_ni_detection_sequence",
        "type": "Requires",
        "description": "VAESDEC requires detection sequence to verify support",
        "evidence_quote": "",
        "source_page": 365
      },
      {
        "source": "vex_encoded_aes_ni_detection_sequence",
        "target": "cpuid_01h_ecx_aes_25_flag",
        "type": "Prerequisite",
        "description": "Detection sequence checks AES[25] flag for support",
        "evidence_quote": "",
        "source_page": 365
      },
      {
        "source": "vex_encoded_aes_ni_detection_sequence",
        "target": "intel_avx_application_support",
        "type": "Prerequisite",
        "description": "Detection requires AVX support check",
        "evidence_quote": "",
        "source_page": 365
      },
      {
        "source": "vpclmulqdq_instruction",
        "target": "vpclmulqdq_detection_sequence",
        "type": "Requires",
        "description": "VPCLMULQDQ requires its detection sequence",
        "evidence_quote": "",
        "source_page": 365
      },
      {
        "source": "vpclmulqdq_detection_sequence",
        "target": "cpuid_01h_ecx_pclmulqdq_1_flag",
        "type": "Prerequisite",
        "description": "Detection checks PCLMULQDQ[1] flag for support",
        "evidence_quote": "",
        "source_page": 365
      },
      {
        "source": "xgetbv_instruction",
        "target": "xcr0_register",
        "type": "Accesses",
        "description": "XGETBV retrieves XCR0 register value",
        "evidence_quote": "",
        "source_page": 365
      },
      {
        "source": "xcr0_register",
        "target": "xmm_ymm_state_support",
        "type": "Indicates",
        "description": "XCR0 state indicates XMM/YMM enablement by OS",
        "evidence_quote": "",
        "source_page": 365
      },
      {
        "source": "vex_encoded_aes_ni_detection_sequence",
        "target": "xgetbv_instruction",
        "type": "Uses",
        "description": "Detection uses XGETBV to check XCR0 state",
        "evidence_quote": "",
        "source_page": 365
      }
    ],
    "communities": [
      {
        "id": "community-0",
        "entity_ids": [
          "128_bit_packed_single_precision_floating_point_data_type",
          "64_bit_mode",
          "64_bit_packed_integer_data",
          "general_purpose_registers",
          "ia_32_addressing_modes",
          "intel_sse_instructions",
          "intel_sse_programming_environment",
          "memory_addressing",
          "memory_operands",
          "mmx_registers",
          "movlps_instruction",
          "movss_instruction",
          "movups_instruction",
          "packed_single_precision_floating_point_data_type",
          "sse2_extensions",
          "sse_sse2_sse3",
          "x87_fpu_mmx_registers",
          "xmm_registers"
        ],
        "summary": "The graph community centers on the Intel® SSE Programming Environment, which encompasses core components such as XMM registers, MMX registers, general-purpose registers, the packed single precision floating-point data type, and Intel SSE instructions. XMM registers (128-bit) are central, operating on packed single precision floating-point data types (including 128-bit packed variants) and are expanded by 64-bit mode (adding XMM8-XMM15) and SSE2 extensions (enabling double precision floating-point and packed integer operations). MMX registers (64-bit) handle 64-bit packed integer data and interoperate with XMM registers via conversion instructions. General-purpose registers, used with IA-32 addressing modes, address memory operands and hold operands for some SSE instructions, while XMM registers cannot address memory. Memory operands are accessed via general-purpose registers, and SSE instructions primarily use XMM registers, with some operating on general-purpose registers.",
        "key_relationships": [
          {
            "source": "intel_sse_programming_environment",
            "target": [
              "xmm_registers",
              "mmx_registers",
              "general_purpose_registers",
              "packed_single_precision_floating_point_data_type",
              "intel_sse_instructions"
            ],
            "type": "includes",
            "description": "Encompasses core components of the SSE execution environment."
          },
          {
            "source": "xmm_registers",
            "target": "packed_single_precision_floating_point_data_type",
            "type": "operates on",
            "description": "Used to process packed or scalar single precision floating-point data."
          },
          {
            "source": "mmx_registers",
            "target": "64_bit_packed_integer_data",
            "type": "operates on",
            "description": "Performs operations on 64-bit packed integer data."
          },
          {
            "source": "general_purpose_registers",
            "target": "ia_32_addressing_modes",
            "type": "used with",
            "description": "Works with IA-32 addressing modes to address memory operands."
          },
          {
            "source": "64_bit_mode",
            "target": "xmm_registers",
            "type": "adds additional",
            "description": "Provides eight additional XMM registers (XMM8-XMM15) via REX prefixes."
          },
          {
            "source": "sse2_extensions",
            "target": "xmm_registers",
            "type": "expands functions of",
            "description": "Enables XMM registers to handle packed/scalar double precision floating-point and packed integer operands."
          },
          {
            "source": "mmx_registers",
            "target": "xmm_registers",
            "type": "interoperates with",
            "description": "Holds operands for operations between MMX and XMM registers, with conversion instructions."
          },
          {
            "source": "xmm_registers",
            "target": "memory_addressing",
            "type": "cannot be used for",
            "description": "Limited to data calculations; memory addressing is done via general-purpose registers."
          }
        ],
        "source_pages": [
          254,
          255,
          257,
          258,
          259
        ]
      },
      {
        "id": "community-1",
        "entity_ids": [
          "denormals_are_zeros_flag",
          "denormals_are_zeros_mode_daz",
          "flush_to_zero_flag",
          "flush_to_zero_mode",
          "fxrstor_instruction",
          "fxsave_instruction",
          "general_protection_exception_#gp",
          "ieee_standard_754",
          "intel_sse_data_movement_instructions",
          "ldmxcsr_instruction",
          "movaps_instruction",
          "mxcsr_register",
          "simd_floating_point_exceptions",
          "simd_floating_point_operations",
          "stmxcsr_instruction"
        ],
        "summary": "This graph community focuses on SIMD floating-point operations and their control via the MXCSR register, a 32-bit control/status register central to managing SIMD behavior. Key elements include MXCSR components like the flush-to-zero flag (bit 15) and denormals-are-zeros flag, which enable performance modes (flush-to-zero mode, denormals-are-zeros mode/DAZ) incompatible with IEEE 754 standards. Instructions such as LDMXCSR, STMXCSR, FXSAVE, and FXRSTOR load/store MXCSR contents, with FXRSTOR/FXSAVE triggering general-protection exceptions (#GP) if reserved bits (16-31) are non-zero. Data movement instructions like MOVAPS also generate #GP on unaligned memory access, while MXCSR contains sticky flags for SIMD floating-point exceptions (bits 0-5).",
        "key_relationships": [
          {
            "source": "mxcsr_register",
            "target": "simd_floating_point_operations",
            "type": "controls",
            "description": "Provides status and control bits for SIMD floating-point operations"
          },
          {
            "source": "mxcsr_register",
            "target": "flush_to_zero_flag",
            "type": "has component",
            "description": "Contains bit 15 (FTZ) enabling flush-to-zero mode"
          },
          {
            "source": "mxcsr_register",
            "target": "denormals_are_zeros_flag",
            "type": "has component",
            "description": "Controls handling of denormal source operands"
          },
          {
            "source": "ldmxcsr_instruction",
            "target": "mxcsr_register",
            "type": "loads",
            "description": "Loads MXCSR contents from memory"
          },
          {
            "source": "fxrstor_instruction",
            "target": "mxcsr_register",
            "type": "loads",
            "description": "Loads MXCSR contents from memory"
          },
          {
            "source": "stmxcsr_instruction",
            "target": "mxcsr_register",
            "type": "stores",
            "description": "Stores MXCSR contents to memory"
          },
          {
            "source": "fxsave_instruction",
            "target": "mxcsr_register",
            "type": "stores",
            "description": "Stores MXCSR contents to memory"
          },
          {
            "source": "mxcsr_register",
            "target": "simd_floating_point_exceptions",
            "type": "contains",
            "description": "Bits 0-5 indicate detected exceptions (sticky flags)"
          },
          {
            "source": "flush_to_zero_mode",
            "target": "ieee_standard_754",
            "type": "Incompatibility",
            "description": "Not compatible with IEEE 754 (rounds underflow results to zero)"
          },
          {
            "source": "denormals_are_zeros_mode_daz",
            "target": "ieee_standard_754",
            "type": "Incompatibility",
            "description": "Not compatible with IEEE 754 (converts denormal operands to zero)"
          },
          {
            "source": "movaps_instruction",
            "target": "general_protection_exception_#gp",
            "type": "Generates",
            "description": "Generates #GP if memory address not 16-byte aligned"
          },
          {
            "source": "fxrstor_instruction",
            "target": "general_protection_exception_#gp",
            "type": "causes",
            "description": "Writing non-zero reserved bits (16-31) triggers #GP"
          }
        ],
        "source_pages": [
          254,
          256,
          257,
          259
        ]
      },
      {
        "id": "community-2",
        "entity_ids": [
          "128_bit_arithmetic_intel_avx_instructions",
          "128_bit_intel_avx_instruction_enhancement",
          "legacy_simd_isa",
          "legacy_simd_non_arithmetic_isa",
          "pcmpeqb",
          "pmaddwd",
          "table_14_7",
          "vex_128_encoding",
          "vex_256_encoding",
          "vi",
          "vpermilpd",
          "vpermilps",
          "vtestpd",
          "vtestps"
        ],
        "summary": "This graph community focuses on the promotion of Legacy SIMD ISA to 128-bit Intel® AVX instructions, including both arithmetic and non-arithmetic components, and the enhancement of 128-bit AVX with new instructions. Legacy SIMD ISA is promoted to 128-bit arithmetic AVX instructions using VEX.128 Encoding, while VEX.256 Encoding does not support most such promotions. Specific legacy instructions (e.g., PMADDWD, PCMPEQB) are supported by VEX.128 but not VEX.256. The 128-bit AVX Instruction Enhancement includes new permute (VPERMILPD, VPERMILPS) and test (VTESTPS, VTESTPD) instructions, and incorporates promoted legacy non-arithmetic SIMD ISA, whose promotion state to VEX.128 is listed in Table 14-7.",
        "key_relationships": [
          {
            "source": "legacy_simd_isa",
            "target": "128_bit_arithmetic_intel_avx_instructions",
            "type": "is promoted to",
            "description": "Legacy SIMD ISA is promoted to 128-bit AVX arithmetic instructions"
          },
          {
            "source": "legacy_simd_isa",
            "target": "vex_128_encoding",
            "type": "uses",
            "description": "Legacy SIMD ISA uses VEX.128 Encoding for promotion to 128-bit AVX"
          },
          {
            "source": "pmaddwd",
            "target": "vex_128_encoding",
            "type": "supported by",
            "description": "PMADDWD (legacy instruction) is supported by VEX.128 Encoding"
          },
          {
            "source": "pmaddwd",
            "target": "vex_256_encoding",
            "type": "not supported by",
            "description": "PMADDWD (legacy instruction) is not supported by VEX.256 Encoding"
          },
          {
            "source": "128_bit_intel_avx_instruction_enhancement",
            "target": "vpermilpd",
            "type": "Includes",
            "description": "128-bit AVX enhancement includes permute instruction VPERMILPD"
          },
          {
            "source": "128_bit_intel_avx_instruction_enhancement",
            "target": "legacy_simd_non_arithmetic_isa",
            "type": "Includes Promoted",
            "description": "128-bit AVX enhancement includes promoted legacy non-arithmetic SIMD ISA"
          },
          {
            "source": "legacy_simd_non_arithmetic_isa",
            "target": "table_14_7",
            "type": "Promotion State Listed In",
            "description": "Legacy non-arithmetic SIMD ISA promotion state to VEX.128 is listed in Table 14-7"
          }
        ],
        "source_pages": [
          360,
          362
        ]
      },
      {
        "id": "community-3",
        "entity_ids": [
          "avx_feature_flag",
          "cpuid_01h_ecx_aes_25_flag",
          "cpuid_01h_ecx_avx_28",
          "cpuid_01h_ecx_xsave_26",
          "intel_avx_application_support",
          "osxsave_feature_flag",
          "supports_avx",
          "vaesdec_instruction",
          "vex_encoded_aes_ni_detection_sequence",
          "xcr0_register",
          "xgetbv",
          "xgetbv_instruction",
          "xmm_ymm_state_support",
          "ymm_state"
        ],
        "summary": "This graph community focuses on detecting hardware and software support for Intel AVX instructions and VEX-encoded AES-NI instructions. Key elements include detection functions (e.g., supports_AVX()), hardware/OS feature flags (e.g., AVX, OSXSAVE), registers (XCR0), instructions (XGETBV), and detection sequences (e.g., VEX-encoded AES-NI detection). It emphasizes checking both hardware capabilities (via CPUID flags) and OS support (via XCR0 register state) to confirm enablement of SIMD states (YMM/XMM) required for these instructions.",
        "key_relationships": [
          {
            "source": "supports_avx",
            "target": [
              "osxsave_feature_flag",
              "avx_feature_flag",
              "xgetbv"
            ],
            "description": "Function checks OS (OSXSAVE) and hardware (AVX) flags, and uses XGETBV to retrieve XCR0 for YMM state verification"
          },
          {
            "source": "vex_encoded_aes_ni_detection_sequence",
            "target": [
              "cpuid_01h_ecx_aes_25_flag",
              "intel_avx_application_support",
              "xgetbv_instruction"
            ],
            "description": "Detection sequence requires AES hardware flag, AVX application support, and uses XGETBV to check XCR0 state"
          },
          {
            "source": "xcr0_register",
            "target": [
              "xmm_ymm_state_support"
            ],
            "description": "Register stores state enablement status, indicating OS support for XMM/YMM states via XGETBV retrieval"
          },
          {
            "source": "vaesdec_instruction",
            "target": [
              "vex_encoded_aes_ni_detection_sequence"
            ],
            "description": "VEX-encoded AES-NI instruction requires the detection sequence to verify support"
          },
          {
            "source": [
              "cpuid_01h_ecx_avx_28",
              "cpuid_01h_ecx_xsave_26"
            ],
            "target": [
              "avx_feature_flag",
              "osxsave_feature_flag"
            ],
            "description": "Hardware CPUID flags alone are insufficient; OS support (via OSXSAVE/XCR0) is required for full AVX/XSAVE enablement"
          }
        ],
        "source_pages": [
          363,
          364,
          365
        ]
      },
      {
        "id": "community-4",
        "entity_ids": [
          "128_bit_vector_processing",
          "branch_handling",
          "cpuid_01h_ecx_avx",
          "cpuid_01h_ecx_osxsave",
          "intel_avx",
          "intra_register_manipulation",
          "non_unit_strided_fetching",
          "variable_blend_instructions",
          "vbroadcastss",
          "vex_encoded_instructions",
          "xrstor",
          "xsave"
        ],
        "summary": "This graph community centers on Intel AVX (Advanced Vector Extensions), a technology providing VEX-encoded data processing instructions for SIMD programming, operating on 256-bit YMM registers. It encompasses capabilities like 128-bit vector processing (handling 128-bit SIMD data with VEX-encoded primitives), non-unit-strided fetching (enabling broadcast/masked move), intra-register manipulation (permuting elements), and branch handling (via variable blend instructions with four-operand syntax). VEX-encoded instructions, a core component, enhance flexibility (e.g., for variable blend instructions) and underpin 128-bit processing. Feature flags include CPUID.01H:ECX.AVX (indicating AVX support) and CPUID.01H:ECX.OSXSAVE (a prerequisite for AVX, implying XSAVE/XRSTOR support for extended state management).",
        "key_relationships": [
          {
            "source": "intel_avx",
            "target": "vex_encoded_instructions",
            "type": "includes",
            "description": "employs VEX prefix encoding for data processing"
          },
          {
            "source": "intel_avx",
            "target": "128_bit_vector_processing",
            "type": "supports",
            "description": "via non-arithmetic primitives with VEX.128 encoding"
          },
          {
            "source": "128_bit_vector_processing",
            "target": "non_unit_strided_fetching",
            "type": "enables",
            "description": "via broadcast and masked move SIMD data fetching primitives"
          },
          {
            "source": "128_bit_vector_processing",
            "target": "intra_register_manipulation",
            "type": "enables",
            "description": "via permute primitives for 128-bit SIMD register data"
          },
          {
            "source": "branch_handling",
            "target": "variable_blend_instructions",
            "type": "employs",
            "description": "four-operand syntax for branch conditions"
          },
          {
            "source": "cpuid_01h_ecx_avx",
            "target": "intel_avx",
            "type": "Indicates Support",
            "description": "flag signals AVX instruction support"
          },
          {
            "source": "cpuid_01h_ecx_osxsave",
            "target": "xsave",
            "type": "Implies Support",
            "description": "OSXSAVE=1 implies XSAVE support for extended state saving"
          }
        ],
        "source_pages": [
          361,
          363
        ]
      },
      {
        "id": "community-5",
        "entity_ids": [
          "cpuid_instruction",
          "cr4_osxsave_bit_18",
          "invalid_opcode_exception_#ud",
          "user_state_components",
          "xcr0",
          "xsave_enabled_features",
          "xsave_feature_set",
          "xsaveopt_instruction",
          "ymm_register_state"
        ],
        "summary": "This graph community focuses on the XSAVE feature set, which manages user state components (e.g., YMM register state) through configuration of CR4.OSXSAVE[bit 18] and XCR0. The CPUID instruction enumerates support for the XSAVE feature set and specific instructions like XSAVEOPT. The XSAVE feature set is enabled only if CR4.OSXSAVE[bit 18] is set, which affects XCR0's state management. XCR0 controls XSAVE-enabled features via bit settings, determining which state components are managed; unenabled features trigger invalid-opcode exceptions (#UD). Additionally, XCR0 enables specific states such as YMM register state when configured appropriately.",
        "key_relationships": [
          {
            "source": "xsave_feature_set",
            "target": "cr4_osxsave_bit_18",
            "type": "Prerequisite",
            "description": "Enabled only if CR4.OSXSAVE[bit 18] is set to 1"
          },
          {
            "source": "cpuid_instruction",
            "target": "xsave_feature_set",
            "type": "Enumerates",
            "description": "Reports support via CPUID.01H:ECX.XSAVE[26] bit"
          },
          {
            "source": "cpuid_instruction",
            "target": "xsaveopt_instruction",
            "type": "Enumerates",
            "description": "Support indicated by CPUID.0DH.01H.EAX[0] bit"
          },
          {
            "source": "xcr0",
            "target": "xsave_enabled_features",
            "type": "Controls",
            "description": "Bit settings determine management of their state components"
          },
          {
            "source": "cr4_osxsave_bit_18",
            "target": "xcr0",
            "type": "Affects",
            "description": "If 0, treats all XCR0 bits as clear for state management"
          },
          {
            "source": "xsave_enabled_features",
            "target": "invalid_opcode_exception_#ud",
            "type": "Causes",
            "description": "Executing unenabled instructions triggers #UD"
          },
          {
            "source": "xcr0",
            "target": "ymm_register_state",
            "type": "Enables",
            "description": "XCR0[2:1] = '11b' enables YMM register state"
          }
        ],
        "source_pages": [
          323,
          363
        ]
      },
      {
        "id": "community-6",
        "entity_ids": [
          "addps",
          "addss",
          "general_purpose_register",
          "movhlps",
          "movhps",
          "movlhps",
          "movmskps",
          "xmm_register"
        ],
        "summary": "This graph community focuses on Intel SSE instructions and registers for single precision floating-point operations. It includes arithmetic instructions (ADDPS: packed addition; ADDSS: scalar addition), data movement instructions (MOVHLPS, MOVHPS, MOVLHPS: transfer data between XMM registers or memory and XMM registers), and mask generation instruction (MOVMSKPS: creates a 4-bit mask from XMM register data). Key registers are XMM registers (primary storage for packed floats) and general-purpose registers (receive masks from MOVMSKPS for branching).",
        "key_relationships": [
          {
            "source": "movhps",
            "target": "xmm_register",
            "type": "Uses",
            "description": "Moves data to/from high quadword of XMM register"
          },
          {
            "source": "movlhps",
            "target": "xmm_register",
            "type": "Uses",
            "description": "Moves data between source and destination XMM registers"
          },
          {
            "source": "movhlps",
            "target": "xmm_register",
            "type": "Uses",
            "description": "Moves data between source and destination XMM registers"
          },
          {
            "source": "movmskps",
            "target": "xmm_register",
            "type": "Uses",
            "description": "Takes input from XMM register containing packed floats"
          },
          {
            "source": "movmskps",
            "target": "general_purpose_register",
            "type": "Outputs to",
            "description": "Transfers 4-bit mask to general-purpose register"
          },
          {
            "source": "addps",
            "target": "xmm_register",
            "type": "Uses",
            "description": "Operates on packed floats stored in XMM registers"
          },
          {
            "source": "addss",
            "target": "xmm_register",
            "type": "Uses",
            "description": "Operates on scalar float in XMM register low doubleword"
          },
          {
            "source": "addps",
            "target": "addss",
            "type": "Variant of",
            "description": "Packed version; ADDSS is scalar variant"
          }
        ],
        "source_pages": [
          260
        ]
      },
      {
        "id": "community-7",
        "entity_ids": [
          "64_bit_simd_integer_instructions",
          "arithmetic_instructions",
          "conversion_instructions",
          "data_movement_instructions",
          "intel_sse_instruction_set",
          "packed_and_scalar_single_precision_floating_point_instructions"
        ],
        "summary": "The graph community centers on the Intel SSE instruction set, which is structured into functional groups and subgroups. It includes the 'packed and scalar single precision floating-point instructions' subgroup, which further contains data movement, arithmetic, and conversion instruction subtypes, as well as the '64-bit SIMD integer instructions' functional group.",
        "key_relationships": [
          {
            "source": "intel_sse_instruction_set",
            "target": "packed_and_scalar_single_precision_floating_point_instructions",
            "type": "Includes Subgroup"
          },
          {
            "source": "packed_and_scalar_single_precision_floating_point_instructions",
            "target": "data_movement_instructions",
            "type": "Includes Subtype"
          },
          {
            "source": "packed_and_scalar_single_precision_floating_point_instructions",
            "target": "arithmetic_instructions",
            "type": "Includes Subtype"
          },
          {
            "source": "intel_sse_instruction_set",
            "target": "64_bit_simd_integer_instructions",
            "type": "Includes Functional Group"
          },
          {
            "source": "packed_and_scalar_single_precision_floating_point_instructions",
            "target": "conversion_instructions",
            "type": "Includes Subtype"
          }
        ],
        "source_pages": [
          258
        ]
      }
    ],
    "statistics": {
      "entities": 124,
      "relationships": 123,
      "communities": 8,
      "density": 0.015604510883818515
    }
  },
  "queries": [
    {
      "id": "concept_sse_environment",
      "category": "concept-detail",
      "question": "What architectural state and data model define the Intel SSE programming environment?",
      "reference": "SSE adds eight 128-bit XMM0-XMM7 registers and the 32-bit MXCSR control/status register, and operates on packed or scalar single-precision floating-point data; 64-bit mode exposes XMM8-XMM15.",
      "gold_pages": [
        254,
        255,
        256,
        257
      ]
    },
    {
      "id": "detail_xmm64",
      "category": "concept-detail",
      "question": "In 64-bit mode, which additional XMM registers become accessible and how are they encoded?",
      "reference": "XMM8 through XMM15 become accessible and are selected with REX prefixes.",
      "gold_pages": [
        255
      ]
    },
    {
      "id": "detail_mxcsr",
      "category": "concept-detail",
      "question": "Which MXCSR bits form the SIMD floating-point rounding-control field?",
      "reference": "MXCSR bits 13 and 14 form the rounding-control (RC) field.",
      "gold_pages": [
        256
      ]
    },
    {
      "id": "concept_avx_features",
      "category": "concept-detail",
      "question": "What broad capabilities distinguish the AVX programming model described here?",
      "reference": "AVX uses VEX-encoded instructions, extends vector processing including 256-bit YMM state, and adds flexible data fetching, manipulation, and branch-support primitives.",
      "gold_pages": [
        361,
        362,
        363
      ]
    },
    {
      "id": "relation_avx_detection",
      "category": "relationship-multi-hop",
      "question": "What complete processor-and-operating-system checks must an application perform before using AVX?",
      "reference": "Check CPUID OSXSAVE bit 27 and AVX bit 28, execute XGETBV with ECX=0, and verify XCR0 bits 2:1 are 11b so both XMM and YMM state are enabled by the OS.",
      "gold_pages": [
        363,
        364
      ],
      "path_hints": [
        "AVX",
        "XCR0"
      ]
    },
    {
      "id": "relation_cpuid_insufficient",
      "category": "relationship-multi-hop",
      "question": "Why is CPUID.AVX alone insufficient proof that AVX instructions can execute?",
      "reference": "The operating system must enable XSAVE/XGETBV and XMM/YMM state management in XCR0; otherwise AVX instructions raise #UD even when CPUID.AVX is set.",
      "gold_pages": [
        323,
        363,
        364
      ],
      "path_hints": [
        "CPUID",
        "YMM"
      ]
    },
    {
      "id": "relation_cr4_xcr0",
      "category": "relationship-multi-hop",
      "question": "How do CR4.OSXSAVE, XGETBV, XCR0, and AVX state availability depend on one another?",
      "reference": "CR4.OSXSAVE enables the XSAVE feature set and application use of XGETBV; XGETBV reads XCR0, whose XMM/YMM bits must be enabled for AVX state and instructions to be available.",
      "gold_pages": [
        323,
        363,
        364
      ],
      "path_hints": [
        "CR4.OSXSAVE",
        "AVX"
      ]
    },
    {
      "id": "relation_xcr0_ud",
      "category": "relationship-multi-hop",
      "question": "What happens when an XSAVE-enabled feature is not fully enabled in XCR0, and how does that explain AVX #UD behavior?",
      "reference": "Instructions for a feature not fully enabled in XCR0 raise invalid-opcode #UD; AVX likewise #UDs when the OS has not enabled both XMM and YMM state even if the processor advertises AVX.",
      "gold_pages": [
        323,
        364
      ],
      "path_hints": [
        "XCR0",
        "#UD"
      ]
    }
  ],
  "results": [
    {
      "id": "raptor:concept_sse_environment",
      "method": "raptor",
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      "question": "What architectural state and data model define the Intel SSE programming environment?",
      "reference": "SSE adds eight 128-bit XMM0-XMM7 registers and the 32-bit MXCSR control/status register, and operates on packed or scalar single-precision floating-point data; 64-bit mode exposes XMM8-XMM15.",
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          "summary": "Intel® Streaming SIMD Extensions (Intel® SSE) is fully compatible with IA-32 processor software, allowing existing software to run unmodified on SSE-incorporating processors. CPUID enhancements enable SSE detection, and SSE is accessible in all IA-32 execution modes (protected, real address, virtual-8086). The chapter describes the SSE programming environment, including XMM registers, packed single precision floating-point data type, and SSE instructions. Additional details are in sections 11.5 (exceptions), 11.6 (application writing), the Intel® 64 and IA-32 Architectures Software Developer’s Manual Volumes 2A-2D (instruction descriptions), and Volume 3A Chapter 16 (OS integration). The SSE execution environment includes eight 128-bit XMM registers (XMM0-XMM7) for packed/scalar single precision floating-point operations; a 32-bit MXCSR register for SIMD floating-point status/control; eight 64-bit MMX registers (MM0-MM7) for packed integer data and XMM operand interaction; and eight 32-bit general-purpose registers for memory addressing (MMX/XMM registers cannot address memory).",
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          "text_preview": "PROGRAMMING WITH INTEL® STREAMING SIMD EXTENSIONS (INTEL® SSE)\n\n\nIntel SSE is fully compatible with all software written for IA-32 processors. All existing software continues to run\ncorrectly, without modification, on processors that incorporate Intel SSE. Enhancements to CPUID permit detection\nof Intel SSE. Intel SSE is accessible from all IA-32 execution modes: protected mode, real address mode, and\nvirtual-8086 mode.\nThe following sections of this chapter describe the programming environment for Intel SSE, including: XMM regis-\nters, the packed single precision floating-point data type, and Intel SSE instructions. For additional information,\nsee:\n•   Section 11.6, “Writing Applications with Intel® SSE and SSE2.”\n•   Section 11.5, “Intel® SSE, SSE2, and SSE3 Exceptions,” describes the exceptions that can be generated with\n    Intel SSE/SSE2/SSE3 instructions.\n•   The Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volumes 2A, 2B, 2C, & 2D, provides a\n    detailed description of these instructions.\n•   Chapter 16, “System Programming for Instruction Set Extensions and Processor Extended States,” in the Intel®\n    64 and IA-32 Architectures Software Developer’s Manua",
          "score": 0.5970227718353271
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          "id": "root",
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          "summary": "The content covers key components of Intel's SIMD (Single Instruction, Multiple Data) architecture and state management, including the Streaming SIMD Extensions (SSE) as a foundational SIMD extension, the promotion of legacy SIMD ISA to 128-bit Intel AVX (Advanced Vector Extensions) instructions, and the XSAVE feature set for managing state components of these extensions.",
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          "summary": "This section covers Intel® Streaming SIMD Extensions (Intel® SSE) programming, focusing on the 128-bit packed single precision floating-point data type, which contains four single precision floating-point values and is operated on in XMM registers or memory. Conversion instructions are provided for converting packed/scalar single precision floating-point values to integers, and between XMM, MMX, and general-purpose bit registers. The 128-bit packed memory operand requires 16-byte boundary alignment, except for MOVUPS (supporting unaligned accesses) and scalar 4-byte memory operands (no alignment requirements). Intel SSE instructions are divided into four functional groups: packed/scalar single precision floating-point, 64-bit SIMD integer, state management, and cacheability control/prefetch/memory ordering. Packed and scalar single precision floating-point instructions are further subgrouped into data movement, arithmetic, logical, comparison, shuffle, and conversion instructions; packed instructions perform SIMD operations on four parallel values in operands.",
          "key_terms": [
            "Intel® Streaming SIMD Extensions (Intel® SSE)",
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            "16-byte boundary alignment",
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            "conversion instructions",
            "MMX registers",
            "general-purpose bit registers",
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            "packed single precision floating-point instructions",
            "scalar single precision floating-point instructions",
            "64-bit SIMD integer instructions",
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            "memory ordering instructions",
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            "arithmetic instructions",
            "logical instructions",
            "comparison instructions",
            "shuffle instructions"
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          "source_pages": [
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          "text_preview": "PROGRAMMING WITH INTEL® STREAMING SIMD EXTENSIONS (INTEL® SSE)\n\n\ninto a double quadword. See Figure 4-3 for the layout of a single precision floating-point value; refer to Section\n4.2.2, “Floating-Point Data Types,” for a detailed description of the single precision floating-point format.\n\n\n\n                                                                              Contains 4 Single Precision\n                                                                              Floating-Point Values\n                  127          96 95         64 63         32 31          0\n\n                        Figure 10-4. 128-Bit Packed Single Precision Floating-Point Data Type\n\nThis 128-bit packed single precision floating-point data type is operated on in the XMM registers or in memory.\nConversion instructions are provided to convert two packed single precision floating-point values into two packed\ndoubleword integers or a scalar single precision floating-point value into a doubleword integer (see Figure 11-8).\nIntel SSE provides conversion instructions between XMM registers and MMX registers, and between XMM registers\nand general-purpose bit registers. See Figure 11-8.\nThe address of a 128-bit p",
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          "id": "leaf-259",
          "level": 0,
          "summary": "This section covers programming with Intel® Streaming SIMD Extensions (Intel® SSE), focusing on single precision floating-point operations and data movement instructions. Packed single precision floating-point operations (Figure 10-5) operate on all four doublewords (X3-X0 and Y3-Y0) of source operands. Scalar single precision floating-point operations (Figure 10-6) act only on the low doublewords (X0 and Y0), with the three most significant doublewords (X1-X3) of the first source operand passed through to the destination. Scalar operations are similar to x87 FPU operations with single precision (24-bit significand) but differ in exponent range (x87 uses 15-bit, SSE uses 8-bit). Intel SSE data movement instructions (10.4.1.1) include MOVAPS (moves aligned packed single precision between XMM registers/memory; requires 16-byte memory alignment, else #GP exception), MOVUPS (same as MOVAPS without alignment requirement), MOVSS (transfers scalar single precision to/from the low doubleword of an XMM register), and MOVLPS (moves two packed single precision to/from the low quadword of an XMM register, leaving the high quadword unchanged).",
          "key_terms": [
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            "16-byte alignment",
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            "24-bit significand",
            "15-bit exponent range",
            "8-bit exponent range"
          ],
          "source_pages": [
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          ],
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          "text_preview": "PROGRAMMING WITH INTEL® STREAMING SIMD EXTENSIONS (INTEL® SSE)\n\n\n\n\n                                X3             X2                  X1               X0\n\n\n\n\n                                     Y3          Y2                  Y1             Y0\n\n\n                                 OP             OP                  OP             OP\n\n\n\n                              X3 OP Y3       X2 OP Y2            X1 OP Y1         X0 OP Y0\n\n                          Figure 10-5. Packed Single Precision Floating-Point Operation\n\nThe scalar single precision floating-point instructions operate on the low (least significant) doublewords of the two\nsource operands (X0 and Y0); see Figure 10-6. The three most significant doublewords (X1, X2, and X3) of the first\nsource operand are passed through to the destination. The scalar operations are similar to the floating-point oper-\nations performed in the x87 FPU data registers with the precision control field in the x87 FPU control word set for\nsingle precision (24-bit significand), except that x87 stack operations use a 15-bit exponent range for the result,\nwhile SSE operations use an 8-bit exponent range.\n\n\n\n                                 X3             X",
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          "id": "leaf-257",
          "level": 0,
          "summary": "The documentation covers programming with Intel® SSE, including flush-to-zero mode (returns zero with sign of true result, sets precision/underflow flags, not IEEE 754 compatible, for performance with common underflows, cleared on power-up/reset). Denormals-Are-Zeros (DAZ) mode (bit 6 of MXCSR; converts denormal operands to zero with original sign before computation, doesn't set DE flag/generate exception, not IEEE 754 compatible, for performance like streaming media, cleared on power-up/reset; introduced in Pentium 4/Xeon with SSE2, compatible with SSE; earlier IA-32/some Pentium 4 have bit 6 reserved; setting unsupported DAZ causes #GP, use FXSAVE's MXCSR_MASK to prevent). SSE compatibility: state (XMM, MXCSR) shared with SSE2/SSE3, instructions compatible (mixable without state saving); XMM registers independent of x87 FPU/MMX (parallel operations possible); FXSAVE/FXRSTOR save/restore SSE/SSE2/SSE3 with x87/MMX state. SSE data types: introduced 128-bit packed single precision floating-point (four 32-bit IEEE values).",
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            "MXCSR register",
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            "DM bit (denormal-operand exception mask bit)",
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            "SSE2 extensions",
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            "FXSAVE instruction",
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            "XMM registers",
            "x87 FPU",
            "MMX registers",
            "128-bit packed single precision floating-point data type"
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          "text_preview": "PROGRAMMING WITH INTEL® STREAMING SIMD EXTENSIONS (INTEL® SSE)\n\n\n•   Returns a zero result with the sign of the true result.\n•   Sets the precision and underflow exception flags.\nIf the underflow exception is not masked, the flush-to-zero bit is ignored.\nThe flush-to-zero mode is not compatible with IEEE Standard 754. The IEEE-mandated masked response to under-\nflow is to deliver the denormalized result (see Section 4.8.3.2, “Normalized and Denormalized Finite Numbers”).\nThe flush-to-zero mode is provided primarily for performance reasons. At the cost of a slight precision loss, faster\nexecution can be achieved for applications where underflows are common and rounding the underflow result to\nzero can be tolerated.\nThe flush-to-zero bit is cleared upon a power-up or reset of the processor, disabling the flush-to-zero mode.\n\n\n10.2.3.4     Denormals-Are-Zeros\nBit 6 (DAZ) of the MXCSR register enables the denormals-are-zeros mode, which controls the processor’s response\nto a SIMD floating-point denormal operand condition. When the denormals-are-zeros flag is set, the processor\nconverts all denormal source operands to a zero with the sign of the original operand before performing any\nco",
          "score": 0.4765234589576721
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      "answer": "The architectural state of the Intel SSE programming environment includes: eight 128-bit XMM registers (XMM0-XMM7) for packed/scalar single precision floating-point operations; a 32-bit MXCSR register for SIMD floating-point status and control; eight 64-bit MMX registers (MM0-MM7) for packed integer data and interaction with XMM operands; and eight 32-bit general-purpose registers for memory addressing (MMX/XMM registers cannot address memory) [254].  \n\nThe data model is defined by the 128-bit packed single precision floating-point data type, which contains four 32-bit IEEE single precision floating-point values, operated on in XMM registers or memory [257, 258]. This data type supports both packed operations (acting on all four parallel values) and scalar operations (acting only on the low doubleword, with higher doublewords passed through) [259]. 128-bit packed memory operands require 16-byte boundary alignment, except for MOVUPS (supporting unaligned accesses) and scalar 4-byte memory operands (no alignment requirements) [258].",
      "query_latency_ms": 14412.293,
      "external_judge": {
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        "score": 4,
        "correct": true,
        "reason": "The answer accurately describes the architectural state and data model of the Intel SSE programming environment, including the XMM registers, MXCSR register, MMX registers, and general-purpose registers. It also correctly explains the data model of 128-bit packed single precision floating-point data type and its operations in XMM registers or memory."
      }
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      "question": "What architectural state and data model define the Intel SSE programming environment?",
      "reference": "SSE adds eight 128-bit XMM0-XMM7 registers and the 32-bit MXCSR control/status register, and operates on packed or scalar single-precision floating-point data; 64-bit mode exposes XMM8-XMM15.",
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                "quote": "Intel SSE instructions use the XMM registers only to operate on packed single precision floating-point operands... Some Intel SSE instructions may be used to operate on general-purpose registers."
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              "A SIMD extension compatible with IA-32 software, accessible in IA-32 execution modes, with a programming environment including registers, data types, and instructions."
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          },
          {
            "id": "mmx_registers",
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              "Involved in conversion instructions with XMM registers"
            ],
            "evidence": [
              {
                "page": 254,
                "quote": "MMX registers — These eight registers... are used to perform operations on 64-bit packed integer data. They are also used to hold operands for some operations performed between the MMX and XMM registers. MMX registers are referenced by the names MM0 through MM7."
              }
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              "32-bit register containing control and status information for Intel SSE, SSE2, and SSE3 SIMD floating-point operations; includes flag and mask bits for SIMD floating-point exceptions and rounding control field for SIMD floating-point operations"
            ],
            "evidence": [
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                "quote": "The 32-bit MXCSR register (see Figure 10-3) contains control and status information for Intel SSE, SSE2, and SSE3 SIMD floating-point operations. This register contains: • Flag and mask bits for SIMD floating-point exceptions. • Rounding control field for SIMD floating-point operations."
              }
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              "Register with flags like DAZ; controls SIMD floating-point behavior"
            ],
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            ],
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                "quote": "Eight 128-bit XMM data registers were introduced into the IA-32 architecture with Intel SSE (see Figure 10-2). These registers can be accessed directly using the names XMM0 to XMM7; and they can be accessed independently from the x87 FPU and MMX registers and the general-purpose registers (that is, they are not aliased to any other of the processor’s registers). Intel SSE instructions use the XMM registers only to operate on packed single precision floating-point operands. SSE2 extensions expand the functions of the XMM registers to operand on packed or scalar double precision floating-point operands and packed integer operands; ... XMM registers can only be used to perform calculations on data; they cannot be used to address memory. Data can be loaded into XMM registers or written from the registers to memory in 32-bit, 64-bit, and 128-bit increments."
              }
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            "target": "mxcsr_register",
            "type": "includes",
            "description": "The Intel SSE programming environment includes the MXCSR register as a component.",
            "evidence_quote": "Figure 10-1 shows the execution environment for Intel SSE. All Intel SSE instructions operate on the XMM registers, MMX registers, and/or memory as follows: ... MXCSR register...",
            "source_page": 254
          },
          {
            "source": "intel_sse_programming_environment",
            "target": "mmx_registers",
            "type": "includes",
            "description": "The Intel SSE programming environment includes MMX registers as a component.",
            "evidence_quote": "Figure 10-1 shows the execution environment for Intel SSE. All Intel SSE instructions operate on the XMM registers, MMX registers, and/or memory as follows: ... MMX registers...",
            "source_page": 254
          },
          {
            "source": "intel_sse_programming_environment",
            "target": "general_purpose_registers",
            "type": "includes",
            "description": "The Intel SSE programming environment includes general-purpose registers as a component.",
            "evidence_quote": "Figure 10-1 shows the execution environment for Intel SSE. All Intel SSE instructions operate on the XMM registers, MMX registers, and/or memory as follows: ... General-purpose registers...",
            "source_page": 254
          },
          {
            "source": "intel_sse_programming_environment",
            "target": "packed_single_precision_floating_point_data_type",
            "type": "includes",
            "description": "The Intel SSE programming environment includes the packed single precision floating-point data type.",
            "evidence_quote": "the programming environment for Intel SSE, including: XMM registers, the packed single precision floating-point data type, and Intel SSE instructions.",
            "source_page": 254
          },
          {
            "source": "intel_sse_programming_environment",
            "target": "intel_sse_instructions",
            "type": "includes",
            "description": "The Intel SSE programming environment includes Intel SSE instructions.",
            "evidence_quote": "the programming environment for Intel SSE, including: XMM registers, the packed single precision floating-point data type, and Intel SSE instructions.",
            "source_page": 254
          },
          {
            "source": "xmm_registers",
            "target": "packed_single_precision_floating_point_data_type",
            "type": "operates on",
            "description": "XMM registers are used to operate on packed or scalar single precision floating-point data.",
            "evidence_quote": "XMM registers — These eight registers... are used to operate on packed or scalar single precision floating-point data.",
            "source_page": 254
          },
          {
            "source": "mmx_registers",
            "target": "xmm_registers",
            "type": "interoperates with",
            "description": "MMX registers hold operands for some operations between MMX and XMM registers.",
            "evidence_quote": "They are also used to hold operands for some operations performed between the MMX and XMM registers.",
            "source_page": 254
          },
          {
            "source": "general_purpose_registers",
            "target": "intel_sse_instructions",
            "type": "holds operands for",
            "description": "General-purpose registers are used to hold operands for some Intel SSE instructions",
            "evidence_quote": "The general-purpose registers are also used to hold operands for some SSE instructions",
            "source_page": 255
          },
          {
            "source": "intel_sse_instructions",
            "target": "xmm_registers",
            "type": "uses",
            "description": "Intel SSE instructions use the XMM registers to operate on packed single precision floating-point operands",
            "evidence_quote": "Intel SSE instructions use the XMM registers only to operate on packed single precision floating-point operands.",
            "source_page": 255
          },
          {
            "source": "mxcsr_control_and_status_register",
            "target": "intel_sse",
            "type": "controls and monitors",
            "description": "MXCSR register contains control and status information for Intel SSE SIMD floating-point operations",
            "evidence_quote": "The 32-bit MXCSR register ... contains control and status information for Intel SSE, SSE2, and SSE3 SIMD floating-point operations.",
            "source_page": 255
          },
          {
            "source": "intel_sse_instructions",
            "target": "general_purpose_registers",
            "type": "operates on",
            "description": "Some Intel SSE instructions may be used to operate on general-purpose registers",
            "evidence_quote": "Some Intel SSE instructions may be used to operate on general-purpose registers.",
            "source_page": 255
          },
          {
            "source": "xmm_registers",
            "target": "mmx_registers",
            "type": "Conversion With",
            "description": "Intel SSE provides conversion instructions between XMM and MMX registers",
            "evidence_quote": "",
            "source_page": 258
          },
          {
            "source": "intel_sse_instruction_set",
            "target": "packed_and_scalar_single_precision_floating_point_instructions",
            "type": "Includes Subgroup",
            "description": "Intel SSE instruction set includes packed and scalar single precision FP instructions subgroup",
            "evidence_quote": "",
            "source_page": 258
          },
          {
            "source": "intel_sse_instruction_set",
            "target": "64_bit_simd_integer_instructions",
            "type": "Includes Functional Group",
            "description": "Intel SSE instruction set includes 64-bit SIMD integer instructions group",
            "evidence_quote": "",
            "source_page": 258
          }
        ],
        "communities": [
          {
            "id": "community-6",
            "entity_ids": [
              "addps",
              "addss",
              "general_purpose_register",
              "movhlps",
              "movhps",
              "movlhps",
              "movmskps",
              "xmm_register"
            ],
            "summary": "This graph community focuses on Intel SSE instructions and registers for single precision floating-point operations. It includes arithmetic instructions (ADDPS: packed addition; ADDSS: scalar addition), data movement instructions (MOVHLPS, MOVHPS, MOVLHPS: transfer data between XMM registers or memory and XMM registers), and mask generation instruction (MOVMSKPS: creates a 4-bit mask from XMM register data). Key registers are XMM registers (primary storage for packed floats) and general-purpose registers (receive masks from MOVMSKPS for branching).",
            "key_relationships": [
              {
                "source": "movhps",
                "target": "xmm_register",
                "type": "Uses",
                "description": "Moves data to/from high quadword of XMM register"
              },
              {
                "source": "movlhps",
                "target": "xmm_register",
                "type": "Uses",
                "description": "Moves data between source and destination XMM registers"
              },
              {
                "source": "movhlps",
                "target": "xmm_register",
                "type": "Uses",
                "description": "Moves data between source and destination XMM registers"
              },
              {
                "source": "movmskps",
                "target": "xmm_register",
                "type": "Uses",
                "description": "Takes input from XMM register containing packed floats"
              },
              {
                "source": "movmskps",
                "target": "general_purpose_register",
                "type": "Outputs to",
                "description": "Transfers 4-bit mask to general-purpose register"
              },
              {
                "source": "addps",
                "target": "xmm_register",
                "type": "Uses",
                "description": "Operates on packed floats stored in XMM registers"
              },
              {
                "source": "addss",
                "target": "xmm_register",
                "type": "Uses",
                "description": "Operates on scalar float in XMM register low doubleword"
              },
              {
                "source": "addps",
                "target": "addss",
                "type": "Variant of",
                "description": "Packed version; ADDSS is scalar variant"
              }
            ],
            "source_pages": [
              260
            ]
          },
          {
            "id": "community-7",
            "entity_ids": [
              "64_bit_simd_integer_instructions",
              "arithmetic_instructions",
              "conversion_instructions",
              "data_movement_instructions",
              "intel_sse_instruction_set",
              "packed_and_scalar_single_precision_floating_point_instructions"
            ],
            "summary": "The graph community centers on the Intel SSE instruction set, which is structured into functional groups and subgroups. It includes the 'packed and scalar single precision floating-point instructions' subgroup, which further contains data movement, arithmetic, and conversion instruction subtypes, as well as the '64-bit SIMD integer instructions' functional group.",
            "key_relationships": [
              {
                "source": "intel_sse_instruction_set",
                "target": "packed_and_scalar_single_precision_floating_point_instructions",
                "type": "Includes Subgroup"
              },
              {
                "source": "packed_and_scalar_single_precision_floating_point_instructions",
                "target": "data_movement_instructions",
                "type": "Includes Subtype"
              },
              {
                "source": "packed_and_scalar_single_precision_floating_point_instructions",
                "target": "arithmetic_instructions",
                "type": "Includes Subtype"
              },
              {
                "source": "intel_sse_instruction_set",
                "target": "64_bit_simd_integer_instructions",
                "type": "Includes Functional Group"
              },
              {
                "source": "packed_and_scalar_single_precision_floating_point_instructions",
                "target": "conversion_instructions",
                "type": "Includes Subtype"
              }
            ],
            "source_pages": [
              258
            ]
          }
        ],
        "explicit_paths": []
      },
      "answer": "The Intel SSE programming environment is defined by the following architectural state and data model:  \n\n### **Architectural State**  \n- **XMM registers**: Eight 128-bit registers (XMM0 through XMM7) used to operate on packed or scalar single precision floating-point data. They are independent of x87 FPU, MMX, and general-purpose registers, and cannot address memory directly [254, 255].  \n- **MMX registers**: Eight 64-bit registers (MM0 through MM7) used for 64-bit packed integer data operations and to hold operands for operations between MMX and XMM registers [254].  \n- **General-purpose registers**: Eight 32-bit registers (EAX, EBX, ECX, EDX, EBP, ESI, EDI, ESP) used to address memory operands and hold operands for some SSE instructions [254, 255].  \n- **MXCSR Control and Status Register**: A 32-bit register containing control and status information for SIMD floating-point operations, including exception flags/masks and rounding control [255].  \n\n### **Data Model**  \n- **Packed single precision floating-point data type**: The primary data type operated on by XMM registers [254].  \n\nEvidence is from [254, 255].",
      "query_latency_ms": 14824.567,
      "external_judge": {
        "id": "graphrag:concept_sse_environment",
        "score": 4,
        "correct": true,
        "reason": "The answer correctly identifies the architectural state and data model of the Intel SSE programming environment, including the XMM registers, MMX registers, general-purpose registers, and MXCSR Control and Status Register. It also correctly describes the primary data type operated on by XMM registers. The answer is well-structured and aligns with the provided reference."
      }
    },
    {
      "id": "raptor:detail_xmm64",
      "method": "raptor",
      "query_id": "detail_xmm64",
      "category": "concept-detail",
      "question": "In 64-bit mode, which additional XMM registers become accessible and how are they encoded?",
      "reference": "XMM8 through XMM15 become accessible and are selected with REX prefixes.",
      "gold_pages": [
        255
      ],
      "retrieved_pages": [
        254,
        255,
        256,
        257,
        258,
        259,
        260,
        361,
        363
      ],
      "citation_recall": 1.0,
      "retrieval_trace": [
        {
          "id": "leaf-255",
          "level": 0,
          "summary": "This section covers programming with Intel® Streaming SIMD Extensions (Intel® SSE), including its behavior in 64-bit and compatibility modes, XMM registers, and the MXCSR control and status register. In compatibility mode, SSE functions like in protected mode; 64-bit mode adds eight additional XMM registers (XMM8-XMM15) accessible via REX prefixes, with memory operands using ModR/M, SIB encoding. Some SSE instructions use general-purpose registers, with REX.W prefix for 64-bit general-purpose registers (ignored if meaningless). Intel SSE introduced eight 128-bit XMM registers (XMM0-XMM7), independent of other registers, used for packed single precision floating-point operands (SSE2 expands to handle packed/scalar double precision floating-point and packed integer operands). XMM registers cannot address memory (done via general-purpose registers) but can load/store data in 32, 64, 128-bit increments; 128-bit store uses 16 consecutive bytes with low-order byte first. The 32-bit MXCSR register contains control/status info for SSE/SSE2/SSE3 SIMD floating-point operations, including exception flag/mask bits and rounding control field.",
          "key_terms": [
            "Intel® Streaming SIMD Extensions (Intel® SSE)",
            "64-bit mode",
            "compatibility mode",
            "XMM registers",
            "XMM0-XMM7",
            "XMM8-XMM15",
            "REX prefixes",
            "ModR/M, SIB encoding",
            "general-purpose registers",
            "128-bit",
            "packed single precision floating-point operands",
            "SSE2",
            "MXCSR control and status register",
            "SIMD floating-point exceptions",
            "rounding control field"
          ],
          "source_pages": [
            255
          ],
          "children": [],
          "text_preview": "PROGRAMMING WITH INTEL® STREAMING SIMD EXTENSIONS (INTEL® SSE)\n\n\n    address memory). The general-purpose registers are also used to hold operands for some SSE instructions and\n    are referenced as EAX, EBX, ECX, EDX, EBP, ESI, EDI, and ESP.\n•   EFLAGS register — This 32-bit register (see Figure 3-7) is used to record result of some compare operations.\n\n\n\n10.2.1      Intel® SSE in 64-Bit Mode and Compatibility Mode\nIn compatibility mode, Intel SSE functions like it does in protected mode. In 64-bit mode, eight additional XMM\nregisters are accessible. Registers XMM8-XMM15 are accessed by using REX prefixes. Memory operands are spec-\nified using the ModR/M, SIB encoding described in Section 3.7.5.\nSome Intel SSE instructions may be used to operate on general-purpose registers. Use the REX.W prefix to access\n64-bit general-purpose registers. Note that if a REX prefix is used when it has no meaning, the prefix is ignored.\n\n\n\n10.2.2      XMM Registers\nEight 128-bit XMM data registers were introduced into the IA-32 architecture with Intel SSE (see Figure 10-2).\nThese registers can be accessed directly using the names XMM0 to XMM7; and they can be accessed independently\nfrom the x87 FPU ",
          "score": 0.7489344477653503
        },
        {
          "id": "parent-0",
          "level": 1,
          "summary": "Intel® Streaming SIMD Extensions (SSE) is fully compatible with IA-32 processor software, enabling unmodified existing software execution on SSE-incorporating processors. It is detectable via CPUID and functional in all IA-32 execution modes (protected, real address, virtual-8086). The SSE programming environment includes eight 128-bit XMM registers (XMM0-XMM7) for packed/scalar single precision floating-point operations (64-bit mode adds eight more, XMM8-XMM15, via REX prefixes), independent of other registers. XMM registers cannot address memory (handled by general-purpose registers) but support loading/storing 32/64/128-bit data, with 128-bit stores using 16 consecutive bytes (low-order byte first). The 32-bit MXCSR register controls/statuses SIMD floating-point operations (SSE/SSE2/SSE3), featuring sticky exception flags (bits 0-5), exception mask bits (bits 7-12, all masked on power-up), rounding control (bits 13-14), Flush-to-zero (bit 15, non-IEEE 754 underflow handling), and Denormals-Are-Zeros (DAZ, bit 6, non-IEEE 754 denormal operand conversion, introduced in SSE2). MXCSR is loaded/stored via LDMXCSR/FXRSTOR and STMXCSR/FXSAVE, with bits 16-31 reserved (writing non-zero causes #GP). SSE state (XMM registers, MXCSR) is shared with SSE2/SSE3, enabling mixed instruction use without state saving, and XMM registers are independent of x87 FPU/MMX registers (parallel operations possible). SSE introduces a 128-bit packed single precision floating-point data type (four 32-bit IEEE values). Key instructions include data movement (e.g., MOVAPS for aligned 128-bit transfers, MOVUPS for unaligned, MOVSS for scalar low doubleword, MOVLPS/MOVHPS for quadword transfers) and arithmetic operations (e.g., ADDPS/SUBPS for packed addition/subtraction, ADDSS/SUBSS for scalar, MULPS/MULSS, DIVPS/DIVSS, reciprocal (RCPPS/RCPSS), square root (SQRTPS/SQRTSS), reciprocal square root (RSQRTPS/RSQRTSS), MAXPS). Packed operations act on all four doublewords of operands, while scalar operations target only the low doubleword (X0/Y0), differing from x87 FPU in exponent range (8-bit vs. x87's 15-bit).",
          "key_relationships": {
            "XMM Registers": "Primary storage for packed/scalar single precision floating-point operands; cannot address memory (memory addressing via general-purpose registers); 8 base registers (XMM0-XMM7) in IA-32 modes, 16 (XMM8-XMM15 added) in 64-bit mode via REX prefixes.",
            "MXCSR Register": "Controls SIMD floating-point operations (SSE/SSE2/SSE3) via exception flags (bits 0-5), mask bits (7-12), rounding control (13-14), Flush-to-zero (15), and DAZ (6); loaded/stored via LDMXCSR/FXRSTOR and STMXCSR/FXSAVE; reserved bits (16-31) cause #GP on non-zero writes.",
            "Data Types": "128-bit packed single precision floating-point (four 32-bit IEEE values) is the core SSE data type, operated on in XMM registers/memory with 32/64/128-bit load/store increments (128-bit stores use 16-byte low-order-first alignment).",
            "Instruction Groups": "SSE instructions include data movement (e.g., MOVAPS/MOVUPS for aligned/unaligned 128-bit transfers, MOVSS for scalar) and arithmetic (e.g., ADDPS/ADDSS for packed/scalar addition, RCPPS for reciprocal, SQRTPS for square root); packed operations act on all four doublewords, scalar on low doubleword.",
            "Compatibility": "SSE state (XMM, MXCSR) is shared with SSE2/SSE3, allowing mixed instruction use; XMM registers are independent of x87 FPU/MMX registers (parallel operations possible); 64-bit mode extends XMM registers and uses REX prefixes for memory operands."
          },
          "source_pages": [
            254,
            255,
            256,
            257,
            258,
            259,
            260
          ],
          "children": [
            "leaf-254",
            "leaf-255",
            "leaf-256",
            "leaf-257",
            "leaf-258",
            "leaf-259",
            "leaf-260"
          ],
          "score": 0.6232326030731201
        },
        {
          "id": "leaf-254",
          "level": 0,
          "summary": "Intel® Streaming SIMD Extensions (Intel® SSE) is fully compatible with IA-32 processor software, allowing existing software to run unmodified on SSE-incorporating processors. CPUID enhancements enable SSE detection, and SSE is accessible in all IA-32 execution modes (protected, real address, virtual-8086). The chapter describes the SSE programming environment, including XMM registers, packed single precision floating-point data type, and SSE instructions. Additional details are in sections 11.5 (exceptions), 11.6 (application writing), the Intel® 64 and IA-32 Architectures Software Developer’s Manual Volumes 2A-2D (instruction descriptions), and Volume 3A Chapter 16 (OS integration). The SSE execution environment includes eight 128-bit XMM registers (XMM0-XMM7) for packed/scalar single precision floating-point operations; a 32-bit MXCSR register for SIMD floating-point status/control; eight 64-bit MMX registers (MM0-MM7) for packed integer data and XMM operand interaction; and eight 32-bit general-purpose registers for memory addressing (MMX/XMM registers cannot address memory).",
          "key_terms": [
            "Intel® Streaming SIMD Extensions (Intel® SSE)",
            "IA-32 processors",
            "CPUID",
            "execution modes",
            "protected mode",
            "real address mode",
            "virtual-8086 mode",
            "programming environment",
            "XMM registers",
            "packed single precision floating-point data type",
            "Intel SSE instructions",
            "MXCSR register",
            "MMX registers",
            "general-purpose registers",
            "SIMD floating-point operations"
          ],
          "source_pages": [
            254
          ],
          "children": [],
          "text_preview": "PROGRAMMING WITH INTEL® STREAMING SIMD EXTENSIONS (INTEL® SSE)\n\n\nIntel SSE is fully compatible with all software written for IA-32 processors. All existing software continues to run\ncorrectly, without modification, on processors that incorporate Intel SSE. Enhancements to CPUID permit detection\nof Intel SSE. Intel SSE is accessible from all IA-32 execution modes: protected mode, real address mode, and\nvirtual-8086 mode.\nThe following sections of this chapter describe the programming environment for Intel SSE, including: XMM regis-\nters, the packed single precision floating-point data type, and Intel SSE instructions. For additional information,\nsee:\n•   Section 11.6, “Writing Applications with Intel® SSE and SSE2.”\n•   Section 11.5, “Intel® SSE, SSE2, and SSE3 Exceptions,” describes the exceptions that can be generated with\n    Intel SSE/SSE2/SSE3 instructions.\n•   The Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volumes 2A, 2B, 2C, & 2D, provides a\n    detailed description of these instructions.\n•   Chapter 16, “System Programming for Instruction Set Extensions and Processor Extended States,” in the Intel®\n    64 and IA-32 Architectures Software Developer’s Manua",
          "score": 0.5433818101882935
        },
        {
          "id": "leaf-361",
          "level": 0,
          "summary": "Covers promotion of legacy SIMD ISA to 128-bit Intel AVX arithmetic instructions (Table 14-5), noting AESDEC, AESDECLAST, AESENC, AESENCLAST, AESIMX, AESKEYGENASSIST have VEX.128 encoding (no VEX.256) with reason 'VI' (Vector Integer not promoted to 256-bit). Also details 128-bit non-arithmetic primitives in Intel AVX, including VEX-encoded instructions with same functionality as SIMD prefix-encoded XMM register instructions, plus enhancements (Table 14-6) like non-unit-strided fetching (broadcast, masked move), intra-register manipulation (permute), branch handling (variable blend with four-operand syntax, packed TEST for floating-point).",
          "key_terms": [
            "AESDEC",
            "AESDECLAST",
            "AESENC",
            "AESENCLAST",
            "AESIMX",
            "AESKEYGENASSIST",
            "VEX.256",
            "VEX.128",
            "VI (Vector Integer)",
            "non-arithmetic primitives",
            "VEX-prefix encoding",
            "SIMD prefixes",
            "128-bit data processing",
            "non-unit-strided fetching",
            "broadcast",
            "masked move",
            "intra-register manipulation",
            "permute",
            "branch handling",
            "variable blend instructions",
            "four-operand syntax",
            "packed TEST instructions",
            "XMM registers",
            "VBROADCASTSS",
            "VMASKMOVPS",
            "VMASKMOVPD"
          ],
          "source_pages": [
            361
          ],
          "children": [],
          "text_preview": "PROGRAMMING WITH INTEL® AVX, FMA, AND INTEL® AVX2\n\n\n          Table 14-5. Promotion of Legacy SIMD ISA to 128-Bit Arithmetic Intel® AVX Instructions (Contd.)\n      VEX.256            VEX.128\n                                                            Instruction                                Reason Not Promoted\n      Encoding           Encoding\n\n no                yes               AESDEC, AESDECLAST                                           VI\n no                yes               AESENC, AESENCLAST                                           VI\n no                yes               AESIMX, AESKEYGENASSIST                                      VI\n\nDescription of Column “Reason not promoted”:\n•     MMX: Instructions referencing MMX registers do not support VEX.\n•     Scalar: Scalar instructions are not promoted to 256-bit.\n•     Integer: Integer instructions are not promoted.\n•     VI: “Vector Integer” instructions are not promoted to 256-bit.\n\n\n\n14.2.4        Non-Arithmetic Primitives for 128-Bit Vector and Scalar Processing\nIntel AVX provides a full complement of data processing instructions that employ VEX-prefix encoding. These VEX-\nencoded instructions generally provide the same f",
          "score": 0.5097677707672119
        },
        {
          "id": "leaf-363",
          "level": 0,
          "summary": "The content includes a continuation of Table 14-7, which lists Legacy SIMD ISA instructions (e.g., PBLENDVB, PBLENDW, PEXTRW/B/D/Q, PINSRB/D/Q) promoted to 128-bit non-arithmetic Intel AVX instructions (VEX.256 encoding: no, VEX.128 encoding: yes) with 'VI' (Vector Integer) as the reason for not being promoted to 256-bit. Section 14.3 covers detection of Intel AVX instructions, requiring checks for OS support (CPUID.01H:ECX.OSXSAVE[27] = 1, XGETBV verifying XCR0[2:1] = '11b' for XMM/YMM state enable) and processor support (CPUID.01H:ECX.AVX[28] = 1), with a recommended sequence involving these steps.",
          "key_terms": [
            "Legacy SIMD ISA",
            "Intel AVX",
            "VEX.256 Encoding",
            "VEX.128 Encoding",
            "PBLENDVB",
            "PBLENDW",
            "PEXTRW",
            "PEXTRB",
            "PEXTRD",
            "PEXTRQ",
            "PINSRB",
            "PINSRD",
            "PINSRQ",
            "VI (Vector Integer)",
            "YMM register state",
            "XGETBV instruction",
            "XSAVE/XRSTOR",
            "CPUID.01H:ECX.OSXSAVE[27]",
            "XCR0[2:1] = '11b'",
            "CPUID.01H:ECX.AVX[28]"
          ],
          "source_pages": [
            363
          ],
          "children": [],
          "text_preview": "PROGRAMMING WITH INTEL® AVX, FMA, AND INTEL® AVX2\n\n\n       Table 14-7. Promotion of Legacy SIMD ISA to 128-Bit Non-Arithmetic Intel® AVX instruction (Contd.)\n     VEX.256            VEX.128\n                                                                Instruction                              Reason Not Promoted\n     Encoding           Encoding\n\nno                yes                  PBLENDVB, PBLENDW                                            VI\nno                yes                  PEXTRW, PEXTRB, PEXTRD, PEXTRQ                               VI\nno                yes                  PINSRB, PINSRD, PINSRQ                                       VI\n\nDescription of column “Reason not promoted”:\n•    MMX: Instructions referencing MMX registers do not support VEX.\n•    Scalar: Scalar instructions are not promoted to 256-bit.\n•    VI: “Vector Integer” instructions are not promoted to 256-bit.\n•    Note 1: MOVLPD/PS and MOVHPD/PS are not promoted to 256-bit. The equivalent functionality are provided\n     by VINSERTF128 and VEXTRACTF128 instructions as the existing instructions have no natural 256b extension\n•    Note 3: It is expected that using 128-bit INSERTPS followed by a VINSERTF1",
          "score": 0.5024088621139526
        }
      ],
      "answer": "In 64-bit mode, eight additional XMM registers (XMM8-XMM15) become accessible. They are encoded via REX prefixes [255].",
      "query_latency_ms": 7839.914,
      "external_judge": {
        "id": "raptor:detail_xmm64",
        "score": 4,
        "correct": true,
        "reason": "The answer correctly states that in 64-bit mode, eight additional XMM registers (XMM8-XMM15) become accessible and are encoded via REX prefixes, which matches the information provided in the reference."
      }
    },
    {
      "id": "graphrag:detail_xmm64",
      "method": "graphrag",
      "query_id": "detail_xmm64",
      "category": "concept-detail",
      "question": "In 64-bit mode, which additional XMM registers become accessible and how are they encoded?",
      "reference": "XMM8 through XMM15 become accessible and are selected with REX prefixes.",
      "gold_pages": [
        255
      ],
      "retrieved_pages": [
        254,
        255,
        256,
        257,
        258,
        259,
        260
      ],
      "citation_recall": 1.0,
      "retrieval_trace": {
        "entities": [
          {
            "id": "128_bit_packed_single_precision_floating_point_data_type",
            "name": "128-bit packed single precision floating-point data type",
            "type": "Data Type",
            "descriptions": [
              "SSE data type with four 32-bit single precision floats packed in 128 bits",
              "Operated on in XMM registers or memory; contains 4 single precision values"
            ],
            "evidence": [],
            "source_pages": [
              257,
              258
            ]
          },
          {
            "id": "64_bit_general_purpose_registers",
            "name": "64-bit general-purpose registers",
            "type": "concept",
            "descriptions": [],
            "evidence": [],
            "source_pages": [
              255
            ]
          },
          {
            "id": "64_bit_mode",
            "name": "64-bit mode",
            "type": "Processor Mode",
            "descriptions": [
              "Mode where Intel SSE has eight additional XMM registers (XMM8-XMM15) accessible via REX prefixes; memory operands use ModR/M, SIB encoding"
            ],
            "evidence": [
              {
                "page": 255,
                "quote": "In 64-bit mode, eight additional XMM registers are accessible. Registers XMM8-XMM15 are accessed by using REX prefixes. Memory operands are specified using the ModR/M, SIB encoding described in Section 3.7.5."
              }
            ],
            "source_pages": [
              255
            ]
          },
          {
            "id": "64_bit_packed_integer_data",
            "name": "64-bit packed integer data",
            "type": "Data Type",
            "descriptions": [
              "A data type operated on by MMX registers."
            ],
            "evidence": [
              {
                "page": 254,
                "quote": "MMX registers... are used to perform operations on 64-bit packed integer data."
              }
            ],
            "source_pages": [
              254
            ]
          },
          {
            "id": "fxrstor_instruction",
            "name": "FXRSTOR instruction",
            "type": "Instruction",
            "descriptions": [
              "Loads MXCSR contents from memory; writing non-zero reserved bits causes #GP",
              "Restores SSE/SSE2/SSE3, x87 FPU, and MMX state"
            ],
            "evidence": [],
            "source_pages": [
              256,
              257
            ]
          },
          {
            "id": "fxsave_instruction",
            "name": "FXSAVE instruction",
            "type": "Instruction",
            "descriptions": [
              "Stores MXCSR contents to memory; writing non-zero reserved bits causes #GP",
              "Saves SSE/SSE2/SSE3, x87 FPU, and MMX state"
            ],
            "evidence": [],
            "source_pages": [
              256,
              257
            ]
          },
          {
            "id": "intel_sse_instructions",
            "name": "Intel SSE instructions",
            "type": "Instruction Set",
            "descriptions": [
              "Instructions part of the Intel SSE programming environment.",
              "Instructions that use XMM registers to operate on packed single precision floating-point operands; some may operate on general-purpose registers"
            ],
            "evidence": [
              {
                "page": 254,
                "quote": "the programming environment for Intel SSE, including: XMM registers, the packed single precision floating-point data type, and Intel SSE instructions."
              },
              {
                "page": 255,
                "quote": "Intel SSE instructions use the XMM registers only to operate on packed single precision floating-point operands... Some Intel SSE instructions may be used to operate on general-purpose registers."
              }
            ],
            "source_pages": [
              254,
              255
            ]
          },
          {
            "id": "intel_sse_programming_environment",
            "name": "Intel® SSE Programming Environment",
            "type": "Programming Environment",
            "descriptions": [
              "The execution environment for Intel SSE, including registers, data types, and instructions."
            ],
            "evidence": [
              {
                "page": 254,
                "quote": "The following sections of this chapter describe the programming environment for Intel SSE, including: XMM registers, the packed single precision floating-point data type, and Intel SSE instructions."
              }
            ],
            "source_pages": [
              254
            ]
          },
          {
            "id": "memory_addressing",
            "name": "memory addressing",
            "type": "concept",
            "descriptions": [],
            "evidence": [],
            "source_pages": [
              255
            ]
          },
          {
            "id": "mmx_registers",
            "name": "MMX registers",
            "type": "Register",
            "descriptions": [
              "Eight 64-bit registers used for 64-bit packed integer data operations and operands between MMX and XMM registers, referenced as MM0 through MM7.",
              "Involved in conversion instructions with XMM registers"
            ],
            "evidence": [
              {
                "page": 254,
                "quote": "MMX registers — These eight registers... are used to perform operations on 64-bit packed integer data. They are also used to hold operands for some operations performed between the MMX and XMM registers. MMX registers are referenced by the names MM0 through MM7."
              }
            ],
            "source_pages": [
              254,
              258
            ]
          },
          {
            "id": "movaps_instruction",
            "name": "MOVAPS instruction",
            "type": "Data Movement Instruction",
            "descriptions": [
              "Transfers four packed single precision floating-point values; requires 16-byte aligned memory address"
            ],
            "evidence": [],
            "source_pages": [
              259
            ]
          },
          {
            "id": "movlps_instruction",
            "name": "MOVLPS instruction",
            "type": "Data Movement Instruction",
            "descriptions": [
              "Moves two packed single precision floating-point values to low quadword of XMM register"
            ],
            "evidence": [],
            "source_pages": [
              259
            ]
          },
          {
            "id": "movss_instruction",
            "name": "MOVSS instruction",
            "type": "Data Movement Instruction",
            "descriptions": [
              "Transfers 32-bit scalar single precision floating-point value between XMM registers and memory"
            ],
            "evidence": [],
            "source_pages": [
              259
            ]
          },
          {
            "id": "movups_instruction",
            "name": "MOVUPS instruction",
            "type": "Instruction",
            "descriptions": [
              "Supports unaligned accesses for 128-bit packed memory operands",
              "Transfers four packed single precision floating-point values; no 16-byte alignment required"
            ],
            "evidence": [],
            "source_pages": [
              258,
              259
            ]
          },
          {
            "id": "packed_single_precision_floating_point_data_type",
            "name": "packed single precision floating-point data type",
            "type": "Data Type",
            "descriptions": [
              "A data type operated on by XMM registers in the Intel SSE programming environment."
            ],
            "evidence": [
              {
                "page": 254,
                "quote": "the programming environment for Intel SSE, including: XMM registers, the packed single precision floating-point data type, and Intel SSE instructions."
              }
            ],
            "source_pages": [
              254
            ]
          },
          {
            "id": "rex_prefixes",
            "name": "REX prefixes",
            "type": "Instruction Prefix",
            "descriptions": [
              "Prefixes used to access XMM8-XMM15 registers in 64-bit mode and 64-bit general-purpose registers; ignored if used when meaningless"
            ],
            "evidence": [
              {
                "page": 255,
                "quote": "Registers XMM8-XMM15 are accessed by using REX prefixes... Use the REX.W prefix to access 64-bit general-purpose registers. Note that if a REX prefix is used when it has no meaning, the prefix is ignored."
              }
            ],
            "source_pages": [
              255
            ]
          },
          {
            "id": "sse2_extensions",
            "name": "SSE2 extensions",
            "type": "Instruction Set Extension",
            "descriptions": [
              "Extensions that expand the functions of the XMM registers to operand on packed or scalar double precision floating-point operands and packed integer operands"
            ],
            "evidence": [
              {
                "page": 255,
                "quote": "SSE2 extensions expand the functions of the XMM registers to operand on packed or scalar double precision floating-point operands and packed integer operands"
              }
            ],
            "source_pages": [
              255
            ]
          },
          {
            "id": "sse_sse2_sse3",
            "name": "SSE/SSE2/SSE3",
            "type": "concept",
            "descriptions": [],
            "evidence": [],
            "source_pages": [
              257
            ]
          },
          {
            "id": "x87_fpu_mmx_registers",
            "name": "x87 FPU/MMX registers",
            "type": "concept",
            "descriptions": [],
            "evidence": [],
            "source_pages": [
              257
            ]
          },
          {
            "id": "xmm8_xmm15",
            "name": "XMM8-XMM15",
            "type": "concept",
            "descriptions": [],
            "evidence": [],
            "source_pages": [
              255
            ]
          },
          {
            "id": "xmm_registers",
            "name": "XMM registers",
            "type": "Register",
            "descriptions": [
              "Eight 128-bit registers used to operate on packed or scalar single precision floating-point data, referenced as XMM0 through XMM7.",
              "Eight 128-bit data registers (XMM0 to XMM7) introduced with Intel SSE; not aliased to other registers; used for packed single precision floating-point operands (SSE), expanded by SSE2 for double precision floating-point and packed integer operands; cannot address memory; data loaded/stored in 32-bit, 64-bit, and 128-bit increments",
              "128-bit registers for SSE/SSE2/SSE3; independent of x87/MMX",
              "Used to operate on 128-bit packed single precision floating-point data types",
              "Used for moving single precision floating-point data in Intel SSE operations"
            ],
            "evidence": [
              {
                "page": 254,
                "quote": "XMM registers — These eight registers... are used to operate on packed or scalar single precision floating-point data... XMM registers are referenced by the names XMM0 through XMM7."
              },
              {
                "page": 255,
                "quote": "Eight 128-bit XMM data registers were introduced into the IA-32 architecture with Intel SSE (see Figure 10-2). These registers can be accessed directly using the names XMM0 to XMM7; and they can be accessed independently from the x87 FPU and MMX registers and the general-purpose registers (that is, they are not aliased to any other of the processor’s registers). Intel SSE instructions use the XMM registers only to operate on packed single precision floating-point operands. SSE2 extensions expand the functions of the XMM registers to operand on packed or scalar double precision floating-point operands and packed integer operands; ... XMM registers can only be used to perform calculations on data; they cannot be used to address memory. Data can be loaded into XMM registers or written from the registers to memory in 32-bit, 64-bit, and 128-bit increments."
              }
            ],
            "source_pages": [
              254,
              255,
              257,
              258,
              259
            ]
          }
        ],
        "relationships": [
          {
            "source": "intel_sse_programming_environment",
            "target": "xmm_registers",
            "type": "includes",
            "description": "The Intel SSE programming environment includes XMM registers as a component.",
            "evidence_quote": "the programming environment for Intel SSE, including: XMM registers, the packed single precision floating-point data type, and Intel SSE instructions.",
            "source_page": 254
          },
          {
            "source": "intel_sse_programming_environment",
            "target": "mmx_registers",
            "type": "includes",
            "description": "The Intel SSE programming environment includes MMX registers as a component.",
            "evidence_quote": "Figure 10-1 shows the execution environment for Intel SSE. All Intel SSE instructions operate on the XMM registers, MMX registers, and/or memory as follows: ... MMX registers...",
            "source_page": 254
          },
          {
            "source": "intel_sse_programming_environment",
            "target": "packed_single_precision_floating_point_data_type",
            "type": "includes",
            "description": "The Intel SSE programming environment includes the packed single precision floating-point data type.",
            "evidence_quote": "the programming environment for Intel SSE, including: XMM registers, the packed single precision floating-point data type, and Intel SSE instructions.",
            "source_page": 254
          },
          {
            "source": "intel_sse_programming_environment",
            "target": "intel_sse_instructions",
            "type": "includes",
            "description": "The Intel SSE programming environment includes Intel SSE instructions.",
            "evidence_quote": "the programming environment for Intel SSE, including: XMM registers, the packed single precision floating-point data type, and Intel SSE instructions.",
            "source_page": 254
          },
          {
            "source": "xmm_registers",
            "target": "packed_single_precision_floating_point_data_type",
            "type": "operates on",
            "description": "XMM registers are used to operate on packed or scalar single precision floating-point data.",
            "evidence_quote": "XMM registers — These eight registers... are used to operate on packed or scalar single precision floating-point data.",
            "source_page": 254
          },
          {
            "source": "mmx_registers",
            "target": "64_bit_packed_integer_data",
            "type": "operates on",
            "description": "MMX registers are used to perform operations on 64-bit packed integer data.",
            "evidence_quote": "MMX registers — These eight registers... are used to perform operations on 64-bit packed integer data.",
            "source_page": 254
          },
          {
            "source": "mmx_registers",
            "target": "xmm_registers",
            "type": "interoperates with",
            "description": "MMX registers hold operands for some operations between MMX and XMM registers.",
            "evidence_quote": "They are also used to hold operands for some operations performed between the MMX and XMM registers.",
            "source_page": 254
          },
          {
            "source": "64_bit_mode",
            "target": "xmm_registers",
            "type": "adds additional",
            "description": "64-bit mode provides eight additional XMM registers (XMM8-XMM15)",
            "evidence_quote": "In 64-bit mode, eight additional XMM registers are accessible. Registers XMM8-XMM15 are accessed by using REX prefixes.",
            "source_page": 255
          },
          {
            "source": "intel_sse_instructions",
            "target": "xmm_registers",
            "type": "uses",
            "description": "Intel SSE instructions use the XMM registers to operate on packed single precision floating-point operands",
            "evidence_quote": "Intel SSE instructions use the XMM registers only to operate on packed single precision floating-point operands.",
            "source_page": 255
          },
          {
            "source": "sse2_extensions",
            "target": "xmm_registers",
            "type": "expands functions of",
            "description": "SSE2 extensions expand the functions of the XMM registers to handle double precision floating-point and packed integer operands",
            "evidence_quote": "SSE2 extensions expand the functions of the XMM registers to operand on packed or scalar double precision floating-point operands and packed integer operands",
            "source_page": 255
          },
          {
            "source": "xmm_registers",
            "target": "memory_addressing",
            "type": "cannot be used for",
            "description": "XMM registers cannot be used to address memory",
            "evidence_quote": "XMM registers can only be used to perform calculations on data; they cannot be used to address memory.",
            "source_page": 255
          },
          {
            "source": "rex_prefixes",
            "target": "xmm8_xmm15",
            "type": "accesses",
            "description": "REX prefixes are used to access XMM8-XMM15 registers in 64-bit mode",
            "evidence_quote": "Registers XMM8-XMM15 are accessed by using REX prefixes.",
            "source_page": 255
          },
          {
            "source": "rex_prefixes",
            "target": "64_bit_general_purpose_registers",
            "type": "accesses",
            "description": "REX.W prefix is used to access 64-bit general-purpose registers",
            "evidence_quote": "Use the REX.W prefix to access 64-bit general-purpose registers.",
            "source_page": 255
          },
          {
            "source": "xmm_registers",
            "target": "sse_sse2_sse3",
            "type": "Shared State",
            "description": "XMM registers are shared state between SSE, SSE2, and SSE3",
            "evidence_quote": "",
            "source_page": 257
          },
          {
            "source": "fxsave_instruction",
            "target": "xmm_registers",
            "type": "Saves",
            "description": "FXSAVE instruction saves XMM registers as part of SSE state",
            "evidence_quote": "",
            "source_page": 257
          },
          {
            "source": "fxrstor_instruction",
            "target": "xmm_registers",
            "type": "Restores",
            "description": "FXRSTOR instruction restores XMM registers as part of SSE state",
            "evidence_quote": "",
            "source_page": 257
          },
          {
            "source": "xmm_registers",
            "target": "x87_fpu_mmx_registers",
            "type": "Independence",
            "description": "XMM registers independent of x87 FPU and MMX; parallel operation possible",
            "evidence_quote": "",
            "source_page": 257
          },
          {
            "source": "128_bit_packed_single_precision_floating_point_data_type",
            "target": "xmm_registers",
            "type": "Operated In",
            "description": "128-bit packed single precision data type is operated on in XMM registers",
            "evidence_quote": "",
            "source_page": 258
          },
          {
            "source": "xmm_registers",
            "target": "mmx_registers",
            "type": "Conversion With",
            "description": "Intel SSE provides conversion instructions between XMM and MMX registers",
            "evidence_quote": "",
            "source_page": 258
          },
          {
            "source": "128_bit_packed_single_precision_floating_point_data_type",
            "target": "movups_instruction",
            "type": "Supported By",
            "description": "MOVUPS instruction supports unaligned accesses for 128-bit packed memory operands",
            "evidence_quote": "",
            "source_page": 258
          },
          {
            "source": "movaps_instruction",
            "target": "xmm_registers",
            "type": "Transfers Data Between",
            "description": "Transfers data between XMM registers and memory",
            "evidence_quote": "",
            "source_page": 259
          },
          {
            "source": "movups_instruction",
            "target": "xmm_registers",
            "type": "Transfers Data Between",
            "description": "Transfers data between XMM registers and memory",
            "evidence_quote": "",
            "source_page": 259
          },
          {
            "source": "movss_instruction",
            "target": "xmm_registers",
            "type": "Transfers Data Between",
            "description": "Transfers scalar value between XMM registers and memory",
            "evidence_quote": "",
            "source_page": 259
          },
          {
            "source": "movlps_instruction",
            "target": "xmm_registers",
            "type": "Moves Data To",
            "description": "Moves two values to low quadword; high quadword unchanged",
            "evidence_quote": "",
            "source_page": 259
          }
        ],
        "communities": [
          {
            "id": "community-0",
            "entity_ids": [
              "128_bit_packed_single_precision_floating_point_data_type",
              "64_bit_mode",
              "64_bit_packed_integer_data",
              "general_purpose_registers",
              "ia_32_addressing_modes",
              "intel_sse_instructions",
              "intel_sse_programming_environment",
              "memory_addressing",
              "memory_operands",
              "mmx_registers",
              "movlps_instruction",
              "movss_instruction",
              "movups_instruction",
              "packed_single_precision_floating_point_data_type",
              "sse2_extensions",
              "sse_sse2_sse3",
              "x87_fpu_mmx_registers",
              "xmm_registers"
            ],
            "summary": "The graph community centers on the Intel® SSE Programming Environment, which encompasses core components such as XMM registers, MMX registers, general-purpose registers, the packed single precision floating-point data type, and Intel SSE instructions. XMM registers (128-bit) are central, operating on packed single precision floating-point data types (including 128-bit packed variants) and are expanded by 64-bit mode (adding XMM8-XMM15) and SSE2 extensions (enabling double precision floating-point and packed integer operations). MMX registers (64-bit) handle 64-bit packed integer data and interoperate with XMM registers via conversion instructions. General-purpose registers, used with IA-32 addressing modes, address memory operands and hold operands for some SSE instructions, while XMM registers cannot address memory. Memory operands are accessed via general-purpose registers, and SSE instructions primarily use XMM registers, with some operating on general-purpose registers.",
            "key_relationships": [
              {
                "source": "intel_sse_programming_environment",
                "target": [
                  "xmm_registers",
                  "mmx_registers",
                  "general_purpose_registers",
                  "packed_single_precision_floating_point_data_type",
                  "intel_sse_instructions"
                ],
                "type": "includes",
                "description": "Encompasses core components of the SSE execution environment."
              },
              {
                "source": "xmm_registers",
                "target": "packed_single_precision_floating_point_data_type",
                "type": "operates on",
                "description": "Used to process packed or scalar single precision floating-point data."
              },
              {
                "source": "mmx_registers",
                "target": "64_bit_packed_integer_data",
                "type": "operates on",
                "description": "Performs operations on 64-bit packed integer data."
              },
              {
                "source": "general_purpose_registers",
                "target": "ia_32_addressing_modes",
                "type": "used with",
                "description": "Works with IA-32 addressing modes to address memory operands."
              },
              {
                "source": "64_bit_mode",
                "target": "xmm_registers",
                "type": "adds additional",
                "description": "Provides eight additional XMM registers (XMM8-XMM15) via REX prefixes."
              },
              {
                "source": "sse2_extensions",
                "target": "xmm_registers",
                "type": "expands functions of",
                "description": "Enables XMM registers to handle packed/scalar double precision floating-point and packed integer operands."
              },
              {
                "source": "mmx_registers",
                "target": "xmm_registers",
                "type": "interoperates with",
                "description": "Holds operands for operations between MMX and XMM registers, with conversion instructions."
              },
              {
                "source": "xmm_registers",
                "target": "memory_addressing",
                "type": "cannot be used for",
                "description": "Limited to data calculations; memory addressing is done via general-purpose registers."
              }
            ],
            "source_pages": [
              254,
              255,
              257,
              258,
              259
            ]
          },
          {
            "id": "community-6",
            "entity_ids": [
              "addps",
              "addss",
              "general_purpose_register",
              "movhlps",
              "movhps",
              "movlhps",
              "movmskps",
              "xmm_register"
            ],
            "summary": "This graph community focuses on Intel SSE instructions and registers for single precision floating-point operations. It includes arithmetic instructions (ADDPS: packed addition; ADDSS: scalar addition), data movement instructions (MOVHLPS, MOVHPS, MOVLHPS: transfer data between XMM registers or memory and XMM registers), and mask generation instruction (MOVMSKPS: creates a 4-bit mask from XMM register data). Key registers are XMM registers (primary storage for packed floats) and general-purpose registers (receive masks from MOVMSKPS for branching).",
            "key_relationships": [
              {
                "source": "movhps",
                "target": "xmm_register",
                "type": "Uses",
                "description": "Moves data to/from high quadword of XMM register"
              },
              {
                "source": "movlhps",
                "target": "xmm_register",
                "type": "Uses",
                "description": "Moves data between source and destination XMM registers"
              },
              {
                "source": "movhlps",
                "target": "xmm_register",
                "type": "Uses",
                "description": "Moves data between source and destination XMM registers"
              },
              {
                "source": "movmskps",
                "target": "xmm_register",
                "type": "Uses",
                "description": "Takes input from XMM register containing packed floats"
              },
              {
                "source": "movmskps",
                "target": "general_purpose_register",
                "type": "Outputs to",
                "description": "Transfers 4-bit mask to general-purpose register"
              },
              {
                "source": "addps",
                "target": "xmm_register",
                "type": "Uses",
                "description": "Operates on packed floats stored in XMM registers"
              },
              {
                "source": "addss",
                "target": "xmm_register",
                "type": "Uses",
                "description": "Operates on scalar float in XMM register low doubleword"
              },
              {
                "source": "addps",
                "target": "addss",
                "type": "Variant of",
                "description": "Packed version; ADDSS is scalar variant"
              }
            ],
            "source_pages": [
              260
            ]
          }
        ],
        "explicit_paths": []
      },
      "answer": "In 64-bit mode, eight additional XMM registers (XMM8-XMM15) become accessible. These registers are accessed by using REX prefixes [255].",
      "query_latency_ms": 7296.012,
      "external_judge": {
        "id": "graphrag:detail_xmm64",
        "score": 4,
        "correct": true,
        "reason": "The answer correctly states that in 64-bit mode, eight additional XMM registers (XMM8-XMM15) become accessible and are accessed using REX prefixes, which is consistent with the information provided in the reference."
      }
    },
    {
      "id": "raptor:detail_mxcsr",
      "method": "raptor",
      "query_id": "detail_mxcsr",
      "category": "concept-detail",
      "question": "Which MXCSR bits form the SIMD floating-point rounding-control field?",
      "reference": "MXCSR bits 13 and 14 form the rounding-control (RC) field.",
      "gold_pages": [
        256
      ],
      "retrieved_pages": [
        254,
        255,
        256,
        257,
        258,
        259,
        260
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        {
          "id": "leaf-256",
          "level": 0,
          "summary": "This section covers programming with Intel® Streaming SIMD Extensions (Intel® SSE), focusing on the MXCSR control/status register. It includes flags such as Flush-to-zero (controlling underflow conditions) and Denormals-are-zeros (handling denormal source operands). The MXCSR register can be loaded from memory using LDMXCSR and FXRSTOR, and stored to memory with STMXCSR and FXSAVE. Bits 16-31 are reserved; writing non-zero values here causes a general-protection exception (#GP). SIMD floating-point mask and flag bits: bits 0-5 are sticky exception flags (cleared by LDMXCSR/FXRSTOR), bits 7-12 are exception mask bits (set on power-up/reset, initially masking all exceptions). Unmasking a mask bit with a set flag does not generate an exception until the next SSE/SSE2/SSE3 instruction detecting the condition. The rounding control field (bits 13-14) controls result rounding of SIMD floating-point instructions. Flush-to-zero (bit 15) enables handling masked underflow conditions.",
          "key_terms": [
            "Intel® Streaming SIMD Extensions (Intel® SSE)",
            "MXCSR control/status register",
            "Flush-to-zero flag",
            "Denormals-are-zeros flag",
            "LDMXCSR",
            "STMXCSR",
            "FXRSTOR",
            "FXSAVE",
            "sticky exception flags",
            "exception mask bits",
            "rounding control field",
            "general-protection exception (#GP)"
          ],
          "source_pages": [
            256
          ],
          "children": [],
          "text_preview": "PROGRAMMING WITH INTEL® STREAMING SIMD EXTENSIONS (INTEL® SSE)\n\n\n•   Flush-to-zero flag that provides a means of controlling underflow conditions on SIMD floating-point operations.\n•   Denormals-are-zeros flag that controls how SIMD floating-point instructions handle denormal source operands.\nThe contents of this register can be loaded from memory with the LDMXCSR and FXRSTOR instructions and stored\nin memory with STMXCSR and FXSAVE.\nBits 16 through 31 of the MXCSR register are reserved and are cleared on a power-up or reset of the processor;\nattempting to write a non-zero value to these bits, using either the FXRSTOR or LDMXCSR instructions, will result\nin a general-protection exception (#GP) being generated.\n\n\n                                    31                                 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0\n\n                                                                          F\n                                                                          T   R   P U O Z D I D P U O Z D I\n                                                 Reserved                                     A\n                                                                          Z   C   M M",
          "score": 0.6377246379852295
        },
        {
          "id": "leaf-260",
          "level": 0,
          "summary": "Covers programming with Intel® Streaming SIMD Extensions (Intel® SSE), including move instructions (MOVHPS, MOVLHPS, MOVHLPS, MOVMSKPS) that transfer packed single precision floating-point values between memory and XMM registers or within XMM registers (affecting high/low quadwords while leaving others unchanged), and arithmetic instructions performing addition, subtraction, multiply, divide, reciprocal, square root, reciprocal of square root, and maximum operations on packed or scalar single precision floating-point values (e.g., ADDPS, SUBPS, ADDSS, SUBSS, MULPS, MULSS, DIVPS, DIVSS, RCPPS, RCPSS, SQRTPS, SQRTSS, RSQRTPS, RSQRTSS, MAXPS).",
          "key_terms": [
            "Intel® Streaming SIMD Extensions (Intel® SSE)",
            "MOVHPS",
            "MOVLHPS",
            "MOVHLPS",
            "MOVMSKPS",
            "packed single precision floating-point",
            "scalar single precision floating-point",
            "XMM register",
            "general-purpose register",
            "ADDPS",
            "SUBPS",
            "ADDSS",
            "SUBSS",
            "MULPS",
            "MULSS",
            "DIVPS",
            "DIVSS",
            "RCPPS",
            "RCPSS",
            "SQRTPS",
            "SQRTSS",
            "RSQRTPS",
            "RSQRTSS",
            "MAXPS"
          ],
          "source_pages": [
            260
          ],
          "children": [],
          "text_preview": "PROGRAMMING WITH INTEL® STREAMING SIMD EXTENSIONS (INTEL® SSE)\n\n\nThe MOVHPS (move high packed single precision floating-point) instruction moves two packed single precision\nfloating-point values from memory to the high quadword of an XMM register and vice versa. The low quadword of\nthe register is left unchanged.\nThe MOVLHPS (move packed single precision floating-point low to high) instruction moves two packed single preci-\nsion floating-point values from the low quadword of the source XMM register into the high quadword of the desti-\nnation XMM register. The low quadword of the destination register is left unchanged.\nThe MOVHLPS (move packed single precision floating-point high to low) instruction moves two packed single preci-\nsion floating-point values from the high quadword of the source XMM register into the low quadword of the desti-\nnation XMM register. The high quadword of the destination register is left unchanged.\nThe MOVMSKPS (move packed single precision floating-point mask) instruction transfers the most significant bit of\neach of the four packed single precision floating-point numbers in an XMM register to a general-purpose register.\nThis 4-bit value can then be used ",
          "score": 0.5690639019012451
        },
        {
          "id": "parent-0",
          "level": 1,
          "summary": "Intel® Streaming SIMD Extensions (SSE) is fully compatible with IA-32 processor software, enabling unmodified existing software execution on SSE-incorporating processors. It is detectable via CPUID and functional in all IA-32 execution modes (protected, real address, virtual-8086). The SSE programming environment includes eight 128-bit XMM registers (XMM0-XMM7) for packed/scalar single precision floating-point operations (64-bit mode adds eight more, XMM8-XMM15, via REX prefixes), independent of other registers. XMM registers cannot address memory (handled by general-purpose registers) but support loading/storing 32/64/128-bit data, with 128-bit stores using 16 consecutive bytes (low-order byte first). The 32-bit MXCSR register controls/statuses SIMD floating-point operations (SSE/SSE2/SSE3), featuring sticky exception flags (bits 0-5), exception mask bits (bits 7-12, all masked on power-up), rounding control (bits 13-14), Flush-to-zero (bit 15, non-IEEE 754 underflow handling), and Denormals-Are-Zeros (DAZ, bit 6, non-IEEE 754 denormal operand conversion, introduced in SSE2). MXCSR is loaded/stored via LDMXCSR/FXRSTOR and STMXCSR/FXSAVE, with bits 16-31 reserved (writing non-zero causes #GP). SSE state (XMM registers, MXCSR) is shared with SSE2/SSE3, enabling mixed instruction use without state saving, and XMM registers are independent of x87 FPU/MMX registers (parallel operations possible). SSE introduces a 128-bit packed single precision floating-point data type (four 32-bit IEEE values). Key instructions include data movement (e.g., MOVAPS for aligned 128-bit transfers, MOVUPS for unaligned, MOVSS for scalar low doubleword, MOVLPS/MOVHPS for quadword transfers) and arithmetic operations (e.g., ADDPS/SUBPS for packed addition/subtraction, ADDSS/SUBSS for scalar, MULPS/MULSS, DIVPS/DIVSS, reciprocal (RCPPS/RCPSS), square root (SQRTPS/SQRTSS), reciprocal square root (RSQRTPS/RSQRTSS), MAXPS). Packed operations act on all four doublewords of operands, while scalar operations target only the low doubleword (X0/Y0), differing from x87 FPU in exponent range (8-bit vs. x87's 15-bit).",
          "key_relationships": {
            "XMM Registers": "Primary storage for packed/scalar single precision floating-point operands; cannot address memory (memory addressing via general-purpose registers); 8 base registers (XMM0-XMM7) in IA-32 modes, 16 (XMM8-XMM15 added) in 64-bit mode via REX prefixes.",
            "MXCSR Register": "Controls SIMD floating-point operations (SSE/SSE2/SSE3) via exception flags (bits 0-5), mask bits (7-12), rounding control (13-14), Flush-to-zero (15), and DAZ (6); loaded/stored via LDMXCSR/FXRSTOR and STMXCSR/FXSAVE; reserved bits (16-31) cause #GP on non-zero writes.",
            "Data Types": "128-bit packed single precision floating-point (four 32-bit IEEE values) is the core SSE data type, operated on in XMM registers/memory with 32/64/128-bit load/store increments (128-bit stores use 16-byte low-order-first alignment).",
            "Instruction Groups": "SSE instructions include data movement (e.g., MOVAPS/MOVUPS for aligned/unaligned 128-bit transfers, MOVSS for scalar) and arithmetic (e.g., ADDPS/ADDSS for packed/scalar addition, RCPPS for reciprocal, SQRTPS for square root); packed operations act on all four doublewords, scalar on low doubleword.",
            "Compatibility": "SSE state (XMM, MXCSR) is shared with SSE2/SSE3, allowing mixed instruction use; XMM registers are independent of x87 FPU/MMX registers (parallel operations possible); 64-bit mode extends XMM registers and uses REX prefixes for memory operands."
          },
          "source_pages": [
            254,
            255,
            256,
            257,
            258,
            259,
            260
          ],
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            "leaf-254",
            "leaf-255",
            "leaf-256",
            "leaf-257",
            "leaf-258",
            "leaf-259",
            "leaf-260"
          ],
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        },
        {
          "id": "leaf-258",
          "level": 0,
          "summary": "This section covers Intel® Streaming SIMD Extensions (Intel® SSE) programming, focusing on the 128-bit packed single precision floating-point data type, which contains four single precision floating-point values and is operated on in XMM registers or memory. Conversion instructions are provided for converting packed/scalar single precision floating-point values to integers, and between XMM, MMX, and general-purpose bit registers. The 128-bit packed memory operand requires 16-byte boundary alignment, except for MOVUPS (supporting unaligned accesses) and scalar 4-byte memory operands (no alignment requirements). Intel SSE instructions are divided into four functional groups: packed/scalar single precision floating-point, 64-bit SIMD integer, state management, and cacheability control/prefetch/memory ordering. Packed and scalar single precision floating-point instructions are further subgrouped into data movement, arithmetic, logical, comparison, shuffle, and conversion instructions; packed instructions perform SIMD operations on four parallel values in operands.",
          "key_terms": [
            "Intel® Streaming SIMD Extensions (Intel® SSE)",
            "128-bit packed single precision floating-point data type",
            "XMM registers",
            "16-byte boundary alignment",
            "MOVUPS instruction",
            "conversion instructions",
            "MMX registers",
            "general-purpose bit registers",
            "Intel SSE instruction set",
            "packed single precision floating-point instructions",
            "scalar single precision floating-point instructions",
            "64-bit SIMD integer instructions",
            "state management instructions",
            "cacheability control instructions",
            "prefetch instructions",
            "memory ordering instructions",
            "data movement instructions",
            "arithmetic instructions",
            "logical instructions",
            "comparison instructions",
            "shuffle instructions"
          ],
          "source_pages": [
            258
          ],
          "children": [],
          "text_preview": "PROGRAMMING WITH INTEL® STREAMING SIMD EXTENSIONS (INTEL® SSE)\n\n\ninto a double quadword. See Figure 4-3 for the layout of a single precision floating-point value; refer to Section\n4.2.2, “Floating-Point Data Types,” for a detailed description of the single precision floating-point format.\n\n\n\n                                                                              Contains 4 Single Precision\n                                                                              Floating-Point Values\n                  127          96 95         64 63         32 31          0\n\n                        Figure 10-4. 128-Bit Packed Single Precision Floating-Point Data Type\n\nThis 128-bit packed single precision floating-point data type is operated on in the XMM registers or in memory.\nConversion instructions are provided to convert two packed single precision floating-point values into two packed\ndoubleword integers or a scalar single precision floating-point value into a doubleword integer (see Figure 11-8).\nIntel SSE provides conversion instructions between XMM registers and MMX registers, and between XMM registers\nand general-purpose bit registers. See Figure 11-8.\nThe address of a 128-bit p",
          "score": 0.5471460819244385
        },
        {
          "id": "leaf-255",
          "level": 0,
          "summary": "This section covers programming with Intel® Streaming SIMD Extensions (Intel® SSE), including its behavior in 64-bit and compatibility modes, XMM registers, and the MXCSR control and status register. In compatibility mode, SSE functions like in protected mode; 64-bit mode adds eight additional XMM registers (XMM8-XMM15) accessible via REX prefixes, with memory operands using ModR/M, SIB encoding. Some SSE instructions use general-purpose registers, with REX.W prefix for 64-bit general-purpose registers (ignored if meaningless). Intel SSE introduced eight 128-bit XMM registers (XMM0-XMM7), independent of other registers, used for packed single precision floating-point operands (SSE2 expands to handle packed/scalar double precision floating-point and packed integer operands). XMM registers cannot address memory (done via general-purpose registers) but can load/store data in 32, 64, 128-bit increments; 128-bit store uses 16 consecutive bytes with low-order byte first. The 32-bit MXCSR register contains control/status info for SSE/SSE2/SSE3 SIMD floating-point operations, including exception flag/mask bits and rounding control field.",
          "key_terms": [
            "Intel® Streaming SIMD Extensions (Intel® SSE)",
            "64-bit mode",
            "compatibility mode",
            "XMM registers",
            "XMM0-XMM7",
            "XMM8-XMM15",
            "REX prefixes",
            "ModR/M, SIB encoding",
            "general-purpose registers",
            "128-bit",
            "packed single precision floating-point operands",
            "SSE2",
            "MXCSR control and status register",
            "SIMD floating-point exceptions",
            "rounding control field"
          ],
          "source_pages": [
            255
          ],
          "children": [],
          "text_preview": "PROGRAMMING WITH INTEL® STREAMING SIMD EXTENSIONS (INTEL® SSE)\n\n\n    address memory). The general-purpose registers are also used to hold operands for some SSE instructions and\n    are referenced as EAX, EBX, ECX, EDX, EBP, ESI, EDI, and ESP.\n•   EFLAGS register — This 32-bit register (see Figure 3-7) is used to record result of some compare operations.\n\n\n\n10.2.1      Intel® SSE in 64-Bit Mode and Compatibility Mode\nIn compatibility mode, Intel SSE functions like it does in protected mode. In 64-bit mode, eight additional XMM\nregisters are accessible. Registers XMM8-XMM15 are accessed by using REX prefixes. Memory operands are spec-\nified using the ModR/M, SIB encoding described in Section 3.7.5.\nSome Intel SSE instructions may be used to operate on general-purpose registers. Use the REX.W prefix to access\n64-bit general-purpose registers. Note that if a REX prefix is used when it has no meaning, the prefix is ignored.\n\n\n\n10.2.2      XMM Registers\nEight 128-bit XMM data registers were introduced into the IA-32 architecture with Intel SSE (see Figure 10-2).\nThese registers can be accessed directly using the names XMM0 to XMM7; and they can be accessed independently\nfrom the x87 FPU ",
          "score": 0.5355687141418457
        }
      ],
      "answer": "The SIMD floating-point rounding-control field in the MXCSR register is formed by bits 13-14 [256].",
      "query_latency_ms": 5377.585,
      "external_judge": {
        "id": "raptor:detail_mxcsr",
        "score": 4,
        "correct": true,
        "reason": "The answer correctly identifies that MXCSR bits 13 and 14 form the rounding-control (RC) field, which is consistent with the information provided in the reference."
      }
    },
    {
      "id": "graphrag:detail_mxcsr",
      "method": "graphrag",
      "query_id": "detail_mxcsr",
      "category": "concept-detail",
      "question": "Which MXCSR bits form the SIMD floating-point rounding-control field?",
      "reference": "MXCSR bits 13 and 14 form the rounding-control (RC) field.",
      "gold_pages": [
        256
      ],
      "retrieved_pages": [
        254,
        255,
        256,
        257,
        259,
        260,
        361
      ],
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      "retrieval_trace": {
        "entities": [
          {
            "id": "128_bit_vector_processing",
            "name": "128-bit vector processing",
            "type": "Processing Type",
            "descriptions": [
              "Handles 128-bit SIMD data with VEX-encoded non-arithmetic primitives"
            ],
            "evidence": [],
            "source_pages": [
              361
            ]
          },
          {
            "id": "denormals_are_zeros_flag",
            "name": "Denormals-are-zeros flag",
            "type": "Flag",
            "descriptions": [
              "Controls handling of denormal source operands in SIMD floating-point instructions"
            ],
            "evidence": [],
            "source_pages": [
              256
            ]
          },
          {
            "id": "denormals_are_zeros_mode_daz",
            "name": "denormals-are-zeros mode (DAZ)",
            "type": "Processor Mode",
            "descriptions": [
              "Converts denormal operands to zero with original sign; improves streaming media performance"
            ],
            "evidence": [],
            "source_pages": [
              257
            ]
          },
          {
            "id": "flush_to_zero_flag",
            "name": "Flush-to-zero flag",
            "type": "Flag",
            "descriptions": [
              "Bit 15 of MXCSR; controls masked underflow response in SIMD floating-point ops"
            ],
            "evidence": [],
            "source_pages": [
              256
            ]
          },
          {
            "id": "fxrstor_instruction",
            "name": "FXRSTOR instruction",
            "type": "Instruction",
            "descriptions": [
              "Loads MXCSR contents from memory; writing non-zero reserved bits causes #GP",
              "Restores SSE/SSE2/SSE3, x87 FPU, and MMX state"
            ],
            "evidence": [],
            "source_pages": [
              256,
              257
            ]
          },
          {
            "id": "fxsave_instruction",
            "name": "FXSAVE instruction",
            "type": "Instruction",
            "descriptions": [
              "Stores MXCSR contents to memory; writing non-zero reserved bits causes #GP",
              "Saves SSE/SSE2/SSE3, x87 FPU, and MMX state"
            ],
            "evidence": [],
            "source_pages": [
              256,
              257
            ]
          },
          {
            "id": "intel_sse",
            "name": "Intel SSE",
            "type": "concept",
            "descriptions": [],
            "evidence": [],
            "source_pages": [
              255
            ]
          },
          {
            "id": "intel_sse_programming_environment",
            "name": "Intel® SSE Programming Environment",
            "type": "Programming Environment",
            "descriptions": [
              "The execution environment for Intel SSE, including registers, data types, and instructions."
            ],
            "evidence": [
              {
                "page": 254,
                "quote": "The following sections of this chapter describe the programming environment for Intel SSE, including: XMM registers, the packed single precision floating-point data type, and Intel SSE instructions."
              }
            ],
            "source_pages": [
              254
            ]
          },
          {
            "id": "intra_register_manipulation",
            "name": "Intra-register manipulation",
            "type": "Data Manipulation Capability",
            "descriptions": [
              "Facilitates permutation of floating-point elements in 128-bit SIMD registers"
            ],
            "evidence": [],
            "source_pages": [
              361
            ]
          },
          {
            "id": "ldmxcsr_instruction",
            "name": "LDMXCSR instruction",
            "type": "Instruction",
            "descriptions": [
              "Loads MXCSR contents from memory; clears exception flags when writing zeros"
            ],
            "evidence": [],
            "source_pages": [
              256
            ]
          },
          {
            "id": "mxcsr_control_and_status_register",
            "name": "MXCSR Control and Status Register",
            "type": "Control Register",
            "descriptions": [
              "32-bit register containing control and status information for Intel SSE, SSE2, and SSE3 SIMD floating-point operations; includes flag and mask bits for SIMD floating-point exceptions and rounding control field for SIMD floating-point operations"
            ],
            "evidence": [
              {
                "page": 255,
                "quote": "The 32-bit MXCSR register (see Figure 10-3) contains control and status information for Intel SSE, SSE2, and SSE3 SIMD floating-point operations. This register contains: • Flag and mask bits for SIMD floating-point exceptions. • Rounding control field for SIMD floating-point operations."
              }
            ],
            "source_pages": [
              255
            ]
          },
          {
            "id": "mxcsr_register",
            "name": "MXCSR register",
            "type": "Register",
            "descriptions": [
              "A 32-bit register providing status and control bits for SIMD floating-point operations.",
              "Control/status register for SIMD floating-point ops with reserved bits 16-31",
              "Register with flags like DAZ; controls SIMD floating-point behavior"
            ],
            "evidence": [
              {
                "page": 254,
                "quote": "MXCSR register — This 32-bit register... provides status and control bits used in SIMD floating-point operations."
              }
            ],
            "source_pages": [
              254,
              256,
              257
            ]
          },
          {
            "id": "simd_floating_point_exceptions",
            "name": "SIMD floating-point exceptions",
            "type": "Exception",
            "descriptions": [
              "Detected by MXCSR bits 0-5; sticky flags remain set until cleared"
            ],
            "evidence": [],
            "source_pages": [
              256
            ]
          },
          {
            "id": "simd_floating_point_operations",
            "name": "SIMD floating-point operations",
            "type": "Operation",
            "descriptions": [
              "Floating-point operations controlled by the MXCSR register's status and control bits."
            ],
            "evidence": [
              {
                "page": 254,
                "quote": "MXCSR register... provides status and control bits used in SIMD floating-point operations."
              }
            ],
            "source_pages": [
              254
            ]
          },
          {
            "id": "sse2",
            "name": "SSE2",
            "type": "concept",
            "descriptions": [],
            "evidence": [],
            "source_pages": [
              255
            ]
          },
          {
            "id": "sse3",
            "name": "SSE3",
            "type": "concept",
            "descriptions": [],
            "evidence": [],
            "source_pages": [
              255
            ]
          },
          {
            "id": "stmxcsr_instruction",
            "name": "STMXCSR instruction",
            "type": "Instruction",
            "descriptions": [
              "Stores MXCSR register contents from processor to memory"
            ],
            "evidence": [],
            "source_pages": [
              256
            ]
          }
        ],
        "relationships": [
          {
            "source": "intel_sse_programming_environment",
            "target": "mxcsr_register",
            "type": "includes",
            "description": "The Intel SSE programming environment includes the MXCSR register as a component.",
            "evidence_quote": "Figure 10-1 shows the execution environment for Intel SSE. All Intel SSE instructions operate on the XMM registers, MMX registers, and/or memory as follows: ... MXCSR register...",
            "source_page": 254
          },
          {
            "source": "mxcsr_register",
            "target": "simd_floating_point_operations",
            "type": "controls",
            "description": "The MXCSR register provides status and control bits used in SIMD floating-point operations.",
            "evidence_quote": "MXCSR register — This 32-bit register... provides status and control bits used in SIMD floating-point operations.",
            "source_page": 254
          },
          {
            "source": "mxcsr_control_and_status_register",
            "target": "intel_sse",
            "type": "controls and monitors",
            "description": "MXCSR register contains control and status information for Intel SSE SIMD floating-point operations",
            "evidence_quote": "The 32-bit MXCSR register ... contains control and status information for Intel SSE, SSE2, and SSE3 SIMD floating-point operations.",
            "source_page": 255
          },
          {
            "source": "mxcsr_control_and_status_register",
            "target": "sse2",
            "type": "controls and monitors",
            "description": "MXCSR register contains control and status information for SSE2 SIMD floating-point operations",
            "evidence_quote": "The 32-bit MXCSR register ... contains control and status information for Intel SSE, SSE2, and SSE3 SIMD floating-point operations.",
            "source_page": 255
          },
          {
            "source": "mxcsr_control_and_status_register",
            "target": "sse3",
            "type": "controls and monitors",
            "description": "MXCSR register contains control and status information for SSE3 SIMD floating-point operations",
            "evidence_quote": "The 32-bit MXCSR register ... contains control and status information for Intel SSE, SSE2, and SSE3 SIMD floating-point operations.",
            "source_page": 255
          },
          {
            "source": "mxcsr_register",
            "target": "flush_to_zero_flag",
            "type": "has component",
            "description": "Contains bit 15 (FTZ) enabling flush-to-zero mode",
            "evidence_quote": "",
            "source_page": 256
          },
          {
            "source": "mxcsr_register",
            "target": "denormals_are_zeros_flag",
            "type": "has component",
            "description": "Controls handling of denormal source operands",
            "evidence_quote": "",
            "source_page": 256
          },
          {
            "source": "ldmxcsr_instruction",
            "target": "mxcsr_register",
            "type": "loads",
            "description": "Loads MXCSR contents from memory",
            "evidence_quote": "",
            "source_page": 256
          },
          {
            "source": "fxrstor_instruction",
            "target": "mxcsr_register",
            "type": "loads",
            "description": "Loads MXCSR contents from memory",
            "evidence_quote": "",
            "source_page": 256
          },
          {
            "source": "stmxcsr_instruction",
            "target": "mxcsr_register",
            "type": "stores",
            "description": "Stores MXCSR contents to memory",
            "evidence_quote": "",
            "source_page": 256
          },
          {
            "source": "fxsave_instruction",
            "target": "mxcsr_register",
            "type": "stores",
            "description": "Stores MXCSR contents to memory",
            "evidence_quote": "",
            "source_page": 256
          },
          {
            "source": "mxcsr_register",
            "target": "simd_floating_point_exceptions",
            "type": "contains",
            "description": "Bits 0-5 indicate detected exceptions (sticky flags)",
            "evidence_quote": "",
            "source_page": 256
          },
          {
            "source": "mxcsr_register",
            "target": "denormals_are_zeros_mode_daz",
            "type": "Enables",
            "description": "Bit 6 of MXCSR register enables denormals-are-zeros mode",
            "evidence_quote": "",
            "source_page": 257
          },
          {
            "source": "128_bit_vector_processing",
            "target": "intra_register_manipulation",
            "type": "enables",
            "description": "via permute primitives for 128-bit SIMD register data",
            "evidence_quote": "",
            "source_page": 361
          }
        ],
        "communities": [
          {
            "id": "community-1",
            "entity_ids": [
              "denormals_are_zeros_flag",
              "denormals_are_zeros_mode_daz",
              "flush_to_zero_flag",
              "flush_to_zero_mode",
              "fxrstor_instruction",
              "fxsave_instruction",
              "general_protection_exception_#gp",
              "ieee_standard_754",
              "intel_sse_data_movement_instructions",
              "ldmxcsr_instruction",
              "movaps_instruction",
              "mxcsr_register",
              "simd_floating_point_exceptions",
              "simd_floating_point_operations",
              "stmxcsr_instruction"
            ],
            "summary": "This graph community focuses on SIMD floating-point operations and their control via the MXCSR register, a 32-bit control/status register central to managing SIMD behavior. Key elements include MXCSR components like the flush-to-zero flag (bit 15) and denormals-are-zeros flag, which enable performance modes (flush-to-zero mode, denormals-are-zeros mode/DAZ) incompatible with IEEE 754 standards. Instructions such as LDMXCSR, STMXCSR, FXSAVE, and FXRSTOR load/store MXCSR contents, with FXRSTOR/FXSAVE triggering general-protection exceptions (#GP) if reserved bits (16-31) are non-zero. Data movement instructions like MOVAPS also generate #GP on unaligned memory access, while MXCSR contains sticky flags for SIMD floating-point exceptions (bits 0-5).",
            "key_relationships": [
              {
                "source": "mxcsr_register",
                "target": "simd_floating_point_operations",
                "type": "controls",
                "description": "Provides status and control bits for SIMD floating-point operations"
              },
              {
                "source": "mxcsr_register",
                "target": "flush_to_zero_flag",
                "type": "has component",
                "description": "Contains bit 15 (FTZ) enabling flush-to-zero mode"
              },
              {
                "source": "mxcsr_register",
                "target": "denormals_are_zeros_flag",
                "type": "has component",
                "description": "Controls handling of denormal source operands"
              },
              {
                "source": "ldmxcsr_instruction",
                "target": "mxcsr_register",
                "type": "loads",
                "description": "Loads MXCSR contents from memory"
              },
              {
                "source": "fxrstor_instruction",
                "target": "mxcsr_register",
                "type": "loads",
                "description": "Loads MXCSR contents from memory"
              },
              {
                "source": "stmxcsr_instruction",
                "target": "mxcsr_register",
                "type": "stores",
                "description": "Stores MXCSR contents to memory"
              },
              {
                "source": "fxsave_instruction",
                "target": "mxcsr_register",
                "type": "stores",
                "description": "Stores MXCSR contents to memory"
              },
              {
                "source": "mxcsr_register",
                "target": "simd_floating_point_exceptions",
                "type": "contains",
                "description": "Bits 0-5 indicate detected exceptions (sticky flags)"
              },
              {
                "source": "flush_to_zero_mode",
                "target": "ieee_standard_754",
                "type": "Incompatibility",
                "description": "Not compatible with IEEE 754 (rounds underflow results to zero)"
              },
              {
                "source": "denormals_are_zeros_mode_daz",
                "target": "ieee_standard_754",
                "type": "Incompatibility",
                "description": "Not compatible with IEEE 754 (converts denormal operands to zero)"
              },
              {
                "source": "movaps_instruction",
                "target": "general_protection_exception_#gp",
                "type": "Generates",
                "description": "Generates #GP if memory address not 16-byte aligned"
              },
              {
                "source": "fxrstor_instruction",
                "target": "general_protection_exception_#gp",
                "type": "causes",
                "description": "Writing non-zero reserved bits (16-31) triggers #GP"
              }
            ],
            "source_pages": [
              254,
              256,
              257,
              259
            ]
          },
          {
            "id": "community-6",
            "entity_ids": [
              "addps",
              "addss",
              "general_purpose_register",
              "movhlps",
              "movhps",
              "movlhps",
              "movmskps",
              "xmm_register"
            ],
            "summary": "This graph community focuses on Intel SSE instructions and registers for single precision floating-point operations. It includes arithmetic instructions (ADDPS: packed addition; ADDSS: scalar addition), data movement instructions (MOVHLPS, MOVHPS, MOVLHPS: transfer data between XMM registers or memory and XMM registers), and mask generation instruction (MOVMSKPS: creates a 4-bit mask from XMM register data). Key registers are XMM registers (primary storage for packed floats) and general-purpose registers (receive masks from MOVMSKPS for branching).",
            "key_relationships": [
              {
                "source": "movhps",
                "target": "xmm_register",
                "type": "Uses",
                "description": "Moves data to/from high quadword of XMM register"
              },
              {
                "source": "movlhps",
                "target": "xmm_register",
                "type": "Uses",
                "description": "Moves data between source and destination XMM registers"
              },
              {
                "source": "movhlps",
                "target": "xmm_register",
                "type": "Uses",
                "description": "Moves data between source and destination XMM registers"
              },
              {
                "source": "movmskps",
                "target": "xmm_register",
                "type": "Uses",
                "description": "Takes input from XMM register containing packed floats"
              },
              {
                "source": "movmskps",
                "target": "general_purpose_register",
                "type": "Outputs to",
                "description": "Transfers 4-bit mask to general-purpose register"
              },
              {
                "source": "addps",
                "target": "xmm_register",
                "type": "Uses",
                "description": "Operates on packed floats stored in XMM registers"
              },
              {
                "source": "addss",
                "target": "xmm_register",
                "type": "Uses",
                "description": "Operates on scalar float in XMM register low doubleword"
              },
              {
                "source": "addps",
                "target": "addss",
                "type": "Variant of",
                "description": "Packed version; ADDSS is scalar variant"
              }
            ],
            "source_pages": [
              260
            ]
          }
        ],
        "explicit_paths": []
      },
      "answer": "The retrieved evidence indicates that the MXCSR register contains a \"rounding control field for SIMD floating-point operations\" [255], but it does not specify which bits form this field. Evidence is incomplete.",
      "query_latency_ms": 8210.996,
      "external_judge": {
        "id": "graphrag:detail_mxcsr",
        "score": 0,
        "correct": false,
        "reason": "The answer incorrectly states that the evidence does not specify which bits form the rounding control field, while the reference clearly indicates that MXCSR bits 13 and 14 form this field."
      }
    },
    {
      "id": "raptor:concept_avx_features",
      "method": "raptor",
      "query_id": "concept_avx_features",
      "category": "concept-detail",
      "question": "What broad capabilities distinguish the AVX programming model described here?",
      "reference": "AVX uses VEX-encoded instructions, extends vector processing including 256-bit YMM state, and adds flexible data fetching, manipulation, and branch-support primitives.",
      "gold_pages": [
        361,
        362,
        363
      ],
      "retrieved_pages": [
        360,
        361,
        362,
        363,
        364,
        365
      ],
      "citation_recall": 1.0,
      "retrieval_trace": [
        {
          "id": "leaf-364",
          "level": 0,
          "summary": "Describes the recommended process for detecting Intel® AVX instructions, including pseudocode for a supports_AVX() function. The process involves using CPUID to check OSXSAVE and AVX feature flags in ECX; if set, XGETBV (with ECX=0) is used to verify the operating system has enabled XMM and YMM state support by checking EAX after AND with 06H. A note warns against relying exclusively on CPUID.01H:ECX.AVX[28] or XSAVE[26], as these indicate hardware support only, not operating system support; without OS-enabled YMM state management, Intel AVX instructions will cause #UD. These steps also apply to enhanced 128-bit SIMD floating-point instructions in Intel AVX (using VEX prefix-encoding) operating on YMM states.",
          "key_terms": [
            "Intel® AVX",
            "detection process",
            "pseudocode",
            "supports_AVX()",
            "CPUID",
            "OSXSAVE",
            "AVX feature flags",
            "ECX",
            "XGETBV",
            "XMM state",
            "YMM state",
            "OS support",
            "hardware support",
            "#UD",
            "enhanced 128-bit SIMD floating-point instructions",
            "VEX prefix-encoding"
          ],
          "source_pages": [
            364
          ],
          "children": [],
          "text_preview": "PROGRAMMING WITH INTEL® AVX, FMA, AND INTEL® AVX2\n\n\nThe following pseudocode illustrates this recommended application Intel AVX detection process:\n\nExample 14-1. Detection of Intel® AVX Instruction\n\nINT supports_AVX()\n{ mov        eax, 1\n   cpuid\n   and       ecx, 018000000H\n   cmp       ecx, 018000000H; check both OSXSAVE and AVX feature flags\n    jne      not_supported\n   ; processor supports AVX instructions and XGETBV is enabled by OS\n   mov       ecx, 0; specify 0 for XCR0 register\n   XGETBV              ; result in EDX:EAX\n   and       eax, 06H\n   cmp       eax, 06H; check OS has enabled both XMM and YMM state support\n   jne       not_supported\n   mov       eax, 1\n   jmp       done\nNOT_SUPPORTED:\n   mov       eax, 0\n   done:\n}\n\n\n                                                          NOTE\n         It is unwise for an application to rely exclusively on CPUID.01H:ECX.AVX[28] or at all on\n         CPUID.01H:ECX.XSAVE[26]: These indicate hardware support but not operating system support. If\n         YMM state management is not enabled by an operating systems, Intel AVX instructions will #UD\n         regardless of CPUID.01H:ECX.AVX[28]. “CPUID.01H:ECX.XSAVE[26] = 1” does not gua",
          "score": 0.524924635887146
        },
        {
          "id": "leaf-363",
          "level": 0,
          "summary": "The content includes a continuation of Table 14-7, which lists Legacy SIMD ISA instructions (e.g., PBLENDVB, PBLENDW, PEXTRW/B/D/Q, PINSRB/D/Q) promoted to 128-bit non-arithmetic Intel AVX instructions (VEX.256 encoding: no, VEX.128 encoding: yes) with 'VI' (Vector Integer) as the reason for not being promoted to 256-bit. Section 14.3 covers detection of Intel AVX instructions, requiring checks for OS support (CPUID.01H:ECX.OSXSAVE[27] = 1, XGETBV verifying XCR0[2:1] = '11b' for XMM/YMM state enable) and processor support (CPUID.01H:ECX.AVX[28] = 1), with a recommended sequence involving these steps.",
          "key_terms": [
            "Legacy SIMD ISA",
            "Intel AVX",
            "VEX.256 Encoding",
            "VEX.128 Encoding",
            "PBLENDVB",
            "PBLENDW",
            "PEXTRW",
            "PEXTRB",
            "PEXTRD",
            "PEXTRQ",
            "PINSRB",
            "PINSRD",
            "PINSRQ",
            "VI (Vector Integer)",
            "YMM register state",
            "XGETBV instruction",
            "XSAVE/XRSTOR",
            "CPUID.01H:ECX.OSXSAVE[27]",
            "XCR0[2:1] = '11b'",
            "CPUID.01H:ECX.AVX[28]"
          ],
          "source_pages": [
            363
          ],
          "children": [],
          "text_preview": "PROGRAMMING WITH INTEL® AVX, FMA, AND INTEL® AVX2\n\n\n       Table 14-7. Promotion of Legacy SIMD ISA to 128-Bit Non-Arithmetic Intel® AVX instruction (Contd.)\n     VEX.256            VEX.128\n                                                                Instruction                              Reason Not Promoted\n     Encoding           Encoding\n\nno                yes                  PBLENDVB, PBLENDW                                            VI\nno                yes                  PEXTRW, PEXTRB, PEXTRD, PEXTRQ                               VI\nno                yes                  PINSRB, PINSRD, PINSRQ                                       VI\n\nDescription of column “Reason not promoted”:\n•    MMX: Instructions referencing MMX registers do not support VEX.\n•    Scalar: Scalar instructions are not promoted to 256-bit.\n•    VI: “Vector Integer” instructions are not promoted to 256-bit.\n•    Note 1: MOVLPD/PS and MOVHPD/PS are not promoted to 256-bit. The equivalent functionality are provided\n     by VINSERTF128 and VEXTRACTF128 instructions as the existing instructions have no natural 256b extension\n•    Note 3: It is expected that using 128-bit INSERTPS followed by a VINSERTF1",
          "score": 0.5134183168411255
        },
        {
          "id": "parent-1",
          "level": 1,
          "summary": "Pages 360-365 detail the promotion of Legacy SIMD ISA to 128-bit Intel AVX instructions (arithmetic and non-arithmetic), 128-bit non-arithmetic AVX enhancements, and detection processes for AVX, VEX-encoded AES, and VPCLMULQDQ. Table 14-5 covers 128-bit arithmetic promotion: most have VEX.128 (yes) and VEX.256 (no), with reasons like 'VI' (Vector Integer), 'Scalar', or 'Integer'; includes AES instructions (e.g., AESDEC) with 'VI' as 256-bit promotion reason. 128-bit non-arithmetic AVX primitives (Table 14-6) offer same functionality as SIMD prefix-encoded XMM instructions plus enhancements (broadcast, masked move, permute, branch handling like variable blend or packed TEST for floating-point). Table 14-7 details remaining non-arithmetic promotion: instructions (e.g., PBLENDVB, PEXTRW) have VEX.128 (yes), VEX.256 (no), with reasons like 'VI', 'MMX', or 'redundant'. Legacy non-arithmetic ISA promoted to VEX-256 also support VEX-128 (Table 14-3). AVX detection requires CPU support (CPUID.01H:ECX.AVX[28] = 1) and OS support (CPUID.01H:ECX.OSXSAVE[27] = 1, XGETBV verifying XCR0[2:1] = '11b'). VEX-encoded AES and VPCLMULQDQ detection build on AVX detection, requiring their specific CPUID flags (AESNI[25] for AES, PCLMULQDQ[1] for VPCLMULQDQ) plus OS-enabled XMM/YMM state via XGETBV.",
          "key_relationships": {
            "Tables": "Table 14-5 (arithmetic promotion), Table 14-6 (128-bit non-arithmetic enhancements), Table 14-7 (remaining non-arithmetic promotion) are core; Table 14-3 notes VEX-256 promoted non-arithmetic ISA also support VEX-128.",
            "Promotion Reasons": "'VI' (Vector Integer) is a common reason for 256-bit non-promotion across arithmetic (Table 14-5) and non-arithmetic (Table 14-7) instructions.",
            "AVX Detection": "Requires both CPU support (CPUID.01H:ECX.AVX[28]) and OS support (OSXSAVE flag + XGETBV XCR0[2:1] = '11b') to avoid #UD.",
            "AES/VPCLMULQDQ Detection": "Build on AVX detection, adding their specific CPUID flags (AESNI[25] for AES, PCLMULQDQ[1] for VPCLMULQDQ) while retaining OS support checks via XGETBV."
          },
          "source_pages": [
            360,
            361,
            362,
            363,
            364,
            365
          ],
          "children": [
            "leaf-360",
            "leaf-361",
            "leaf-362",
            "leaf-363",
            "leaf-364",
            "leaf-365"
          ],
          "score": 0.5042107701301575
        },
        {
          "id": "leaf-361",
          "level": 0,
          "summary": "Covers promotion of legacy SIMD ISA to 128-bit Intel AVX arithmetic instructions (Table 14-5), noting AESDEC, AESDECLAST, AESENC, AESENCLAST, AESIMX, AESKEYGENASSIST have VEX.128 encoding (no VEX.256) with reason 'VI' (Vector Integer not promoted to 256-bit). Also details 128-bit non-arithmetic primitives in Intel AVX, including VEX-encoded instructions with same functionality as SIMD prefix-encoded XMM register instructions, plus enhancements (Table 14-6) like non-unit-strided fetching (broadcast, masked move), intra-register manipulation (permute), branch handling (variable blend with four-operand syntax, packed TEST for floating-point).",
          "key_terms": [
            "AESDEC",
            "AESDECLAST",
            "AESENC",
            "AESENCLAST",
            "AESIMX",
            "AESKEYGENASSIST",
            "VEX.256",
            "VEX.128",
            "VI (Vector Integer)",
            "non-arithmetic primitives",
            "VEX-prefix encoding",
            "SIMD prefixes",
            "128-bit data processing",
            "non-unit-strided fetching",
            "broadcast",
            "masked move",
            "intra-register manipulation",
            "permute",
            "branch handling",
            "variable blend instructions",
            "four-operand syntax",
            "packed TEST instructions",
            "XMM registers",
            "VBROADCASTSS",
            "VMASKMOVPS",
            "VMASKMOVPD"
          ],
          "source_pages": [
            361
          ],
          "children": [],
          "text_preview": "PROGRAMMING WITH INTEL® AVX, FMA, AND INTEL® AVX2\n\n\n          Table 14-5. Promotion of Legacy SIMD ISA to 128-Bit Arithmetic Intel® AVX Instructions (Contd.)\n      VEX.256            VEX.128\n                                                            Instruction                                Reason Not Promoted\n      Encoding           Encoding\n\n no                yes               AESDEC, AESDECLAST                                           VI\n no                yes               AESENC, AESENCLAST                                           VI\n no                yes               AESIMX, AESKEYGENASSIST                                      VI\n\nDescription of Column “Reason not promoted”:\n•     MMX: Instructions referencing MMX registers do not support VEX.\n•     Scalar: Scalar instructions are not promoted to 256-bit.\n•     Integer: Integer instructions are not promoted.\n•     VI: “Vector Integer” instructions are not promoted to 256-bit.\n\n\n\n14.2.4        Non-Arithmetic Primitives for 128-Bit Vector and Scalar Processing\nIntel AVX provides a full complement of data processing instructions that employ VEX-prefix encoding. These VEX-\nencoded instructions generally provide the same f",
          "score": 0.4983903765678406
        },
        {
          "id": "leaf-360",
          "level": 0,
          "summary": "This page continues Table 14-5, which details the promotion of Legacy SIMD ISA to 128-bit Arithmetic Intel® AVX Instructions. The table includes columns for VEX.256 Encoding (mostly 'no'), VEX.128 Encoding (mostly 'yes'), specific instructions, and reasons for not being promoted (e.g., 'VI', 'Scalar', 'Integer'). Relevant CPUID flags are also noted (e.g., CPUID.01H:ECX.SSSE3[9], SSE4_1[19], POPCNT[23], SSE4_2[20], PCLMULQDQ[1], AESNI[25]).",
          "key_terms": [
            "Legacy SIMD ISA",
            "128-Bit Arithmetic Intel® AVX Instructions",
            "VEX.256 Encoding",
            "VEX.128 Encoding",
            "Table 14-5",
            "CPUID.01H:ECX.SSSE3[9]",
            "CPUID.01H:ECX.SSE4_1[19]",
            "CPUID.01H:ECX.POPCNT[23]",
            "CPUID.01H:ECX.SSE4_2[20]",
            "CPUID.01H:ECX.PCLMULQDQ[1]",
            "CPUID.01H:ECX.AESNI[25]",
            "VI",
            "Scalar",
            "Integer",
            "PMADDWD",
            "PMADDUBSW",
            "PAVGB",
            "PAVGW",
            "PMULUDQ",
            "PCMPEQB",
            "PCMPEQW",
            "PCMPEQD",
            "PMULLW",
            "PMULHUW",
            "PMULHW",
            "PSUBSW",
            "PADDSW",
            "PSADBW",
            "PADDUSB",
            "PADDUSW",
            "PADDSB",
            "PSUBUSB",
            "PSUBUSW",
            "PSUBSB",
            "PMINUB",
            "PMINSW",
            "PMAXUB",
            "PMAXSW",
            "PADDB",
            "PADDW",
            "PADDD",
            "PADDQ",
            "PSUBB",
            "PSUBW",
            "PSUBD",
            "PSUBQ",
            "PSLLW",
            "PSLLD",
            "PSLLQ",
            "PSRAW",
            "PSRLW",
            "PSRLD",
            "PSRLQ",
            "PSRAD",
            "PHSUBW",
            "PHSUBD",
            "PHSUBSW",
            "PHADDW",
            "PHADDD",
            "PHADDSW",
            "PMULHRSW",
            "PSIGNB",
            "PSIGNW",
            "PSIGND",
            "PABSB",
            "PABSW",
            "PABSD",
            "DPPD",
            "PHMINPOSUW",
            "MPSADBW",
            "PMAXSB",
            "PMAXSD",
            "PMAXUD",
            "PMINSB",
            "PMINSD",
            "PMINUD",
            "PMAXUW",
            "PMINUW",
            "PMOVSXxx",
            "PMOVZXxx",
            "PMULDQ",
            "PMULLD",
            "ROUNDSD",
            "ROUNDSS",
            "POPCNT",
            "PCMPGTQ",
            "CRC32",
            "PCMPESTRI",
            "PCMPESTRM",
            "PCMPISTRI",
            "PCMPISTRM",
            "PCLMULQDQ"
          ],
          "source_pages": [
            360
          ],
          "children": [],
          "text_preview": "PROGRAMMING WITH INTEL® AVX, FMA, AND INTEL® AVX2\n\n\n          Table 14-5. Promotion of Legacy SIMD ISA to 128-Bit Arithmetic Intel® AVX Instructions (Contd.)\n      VEX.256           VEX.128\n                                                          Instruction                      Reason Not Promoted\n      Encoding          Encoding\n no               yes              PMADDWD, PMADDUBSW                                 VI\n no               yes              PAVGB, PAVGW, PMULUDQ                              VI\n no               yes              PCMPEQB, PCMPEQW, PCMPEQD                          VI\n no               yes              PMULLW, PMULHUW, PMULHW                            VI\n no               yes              PSUBSW, PADDSW, PSADBW                             VI\n no               yes              PADDUSB, PADDUSW, PADDSB                           VI\n no               yes              PSUBUSB, PSUBUSW, PSUBSB                           VI\n no               yes              PMINUB, PMINSW                                     VI\n no               yes              PMAXUB, PMAXSW                                     VI\n no               yes              PADDB, PADDW, PADDD, PADDQ    ",
          "score": 0.4711237847805023
        }
      ],
      "answer": "The AVX programming model described here is distinguished by several broad capabilities:  \n\n1. **Promotion of Legacy SIMD ISA to 128-bit AVX Instructions**: Both arithmetic and non-arithmetic legacy SIMD instructions are promoted to 128-bit Intel AVX instructions using VEX prefix encoding. This includes instructions like AESDEC, AESENC, PBLENDVB, and PEXTRW, with most supporting VEX.128 encoding (and limited VEX.256 encoding, often due to reasons like \"VI\" [Vector Integer], \"Scalar\", or \"Integer\") [360, 361, 363, parent-1 (360-365)].  \n\n2. **128-bit Non-Arithmetic AVX Enhancements**: VEX-encoded 128-bit non-arithmetic primitives offer the same functionality as legacy SIMD prefix-encoded XMM instructions, plus enhancements such as non-unit-strided fetching (broadcast, masked move), intra-register manipulation (permute), and improved branch handling (e.g., variable blend with four-operand syntax, packed TEST for floating-point) [361, parent-1 (360-365)].  \n\n3. **VEX Prefix Encoding Support**: The model leverages VEX prefix encoding for these promoted and enhanced instructions, enabling extended functionality while maintaining compatibility with legacy SIMD operations [361, 363, parent-1 (360-365)].",
      "query_latency_ms": 15672.295,
      "external_judge": {
        "id": "raptor:concept_avx_features",
        "score": 4,
        "correct": true,
        "reason": "The answer accurately describes the broad capabilities that distinguish the AVX programming model, including the promotion of legacy SIMD ISA to 128-bit AVX instructions, 128-bit non-arithmetic AVX enhancements, VEX prefix encoding support, and other features like non-unit-strided fetching, intra-register manipulation, and improved branch handling. The answer is detailed and aligns with the provided reference."
      }
    },
    {
      "id": "graphrag:concept_avx_features",
      "method": "graphrag",
      "query_id": "concept_avx_features",
      "category": "concept-detail",
      "question": "What broad capabilities distinguish the AVX programming model described here?",
      "reference": "AVX uses VEX-encoded instructions, extends vector processing including 256-bit YMM state, and adds flexible data fetching, manipulation, and branch-support primitives.",
      "gold_pages": [
        361,
        362,
        363
      ],
      "retrieved_pages": [
        360,
        361,
        362,
        363,
        364,
        365
      ],
      "citation_recall": 1.0,
      "retrieval_trace": {
        "entities": [
          {
            "id": "128_bit_intel_avx_instruction_enhancement",
            "name": "128-bit Intel® AVX Instruction Enhancement",
            "type": "Instruction Set",
            "descriptions": [
              "Enhanced 128-bit AVX instructions including permute and test"
            ],
            "evidence": [],
            "source_pages": [
              362
            ]
          },
          {
            "id": "avx_feature_flag",
            "name": "AVX feature flag",
            "type": "Feature Flag",
            "descriptions": [
              "Indicates hardware support for AVX instructions"
            ],
            "evidence": [],
            "source_pages": [
              364
            ]
          },
          {
            "id": "cpuid_01h_ecx_avx",
            "name": "CPUID.01H:ECX.AVX",
            "type": "Feature Flag",
            "descriptions": [
              "CPUID flag indicating AVX instruction support"
            ],
            "evidence": [],
            "source_pages": [
              363
            ]
          },
          {
            "id": "cpuid_01h_ecx_avx_28",
            "name": "CPUID.01H:ECX.AVX[28]",
            "type": "CPUID Feature Flag",
            "descriptions": [
              "Hardware support indicator for Intel AVX"
            ],
            "evidence": [],
            "source_pages": [
              364
            ]
          },
          {
            "id": "intel_avx",
            "name": "Intel AVX",
            "type": "Technology",
            "descriptions": [
              "Provides VEX-encoded data processing instructions for SIMD programming",
              "Instruction set operating on 256-bit YMM register state"
            ],
            "evidence": [],
            "source_pages": [
              361,
              363
            ]
          },
          {
            "id": "intel_avx_application_support",
            "name": "Intel AVX application support",
            "type": "concept",
            "descriptions": [],
            "evidence": [],
            "source_pages": [
              365
            ]
          },
          {
            "id": "legacy_simd_isa",
            "name": "Legacy SIMD ISA",
            "type": "ISA",
            "descriptions": [
              "Source ISA promoted to 128-bit AVX instructions"
            ],
            "evidence": [],
            "source_pages": [
              360
            ]
          },
          {
            "id": "legacy_simd_non_arithmetic_isa",
            "name": "Legacy SIMD non-arithmetic ISA",
            "type": "ISA Component",
            "descriptions": [
              "Legacy SIMD instructions without arithmetic operations"
            ],
            "evidence": [],
            "source_pages": [
              362
            ]
          },
          {
            "id": "osxsave_feature_flag",
            "name": "OSXSAVE feature flag",
            "type": "Feature Flag",
            "descriptions": [
              "Indicates OS support for XSAVE functionality"
            ],
            "evidence": [],
            "source_pages": [
              364
            ]
          },
          {
            "id": "pcmpeqb",
            "name": "PCMPEQB",
            "type": "Instruction",
            "descriptions": [
              "Legacy SIMD instruction with VEX.128 support"
            ],
            "evidence": [],
            "source_pages": [
              360
            ]
          },
          {
            "id": "pmaddwd",
            "name": "PMADDWD",
            "type": "Instruction",
            "descriptions": [
              "Legacy SIMD instruction promoted via VEX.128"
            ],
            "evidence": [],
            "source_pages": [
              360
            ]
          },
          {
            "id": "supports_avx",
            "name": "supports_AVX()",
            "type": "Function",
            "descriptions": [
              "Function to detect Intel AVX instruction support"
            ],
            "evidence": [],
            "source_pages": [
              364
            ]
          },
          {
            "id": "vex_128_encoding",
            "name": "VEX.128 Encoding",
            "type": "VEX Encoding",
            "descriptions": [
              "Encoding supporting legacy SIMD promotion to 128-bit AVX",
              "128-bit VEX encoding for AVX instructions"
            ],
            "evidence": [],
            "source_pages": [
              360,
              362
            ]
          },
          {
            "id": "vex_encoded_aes_ni_detection_sequence",
            "name": "VEX-encoded AES-NI detection sequence",
            "type": "Detection Sequence",
            "descriptions": [
              "Combines AES flag check and Intel AVX application support check"
            ],
            "evidence": [],
            "source_pages": [
              365
            ]
          },
          {
            "id": "vpermilpd",
            "name": "VPERMILPD",
            "type": "Instruction",
            "descriptions": [
              "Permute double precision floating-point values with controls"
            ],
            "evidence": [],
            "source_pages": [
              362
            ]
          },
          {
            "id": "vpermilps",
            "name": "VPERMILPS",
            "type": "Instruction",
            "descriptions": [
              "Permute single precision floating-point values with controls"
            ],
            "evidence": [],
            "source_pages": [
              362
            ]
          },
          {
            "id": "vtestpd",
            "name": "VTESTPD",
            "type": "Instruction",
            "descriptions": [
              "Set ZF/CF based on packed double precision sign bits"
            ],
            "evidence": [],
            "source_pages": [
              362
            ]
          },
          {
            "id": "vtestps",
            "name": "VTESTPS",
            "type": "Instruction",
            "descriptions": [
              "Set ZF/CF based on packed single precision sign bits"
            ],
            "evidence": [],
            "source_pages": [
              362
            ]
          },
          {
            "id": "xgetbv",
            "name": "XGETBV",
            "type": "Instruction",
            "descriptions": [
              "Instruction to check enabled state in XCR0",
              "Instruction to retrieve XCR0 register value"
            ],
            "evidence": [],
            "source_pages": [
              363,
              364
            ]
          },
          {
            "id": "ymm_state",
            "name": "YMM state",
            "type": "CPU State",
            "descriptions": [
              "SIMD state used by Intel AVX instructions"
            ],
            "evidence": [],
            "source_pages": [
              364
            ]
          }
        ],
        "relationships": [
          {
            "source": "legacy_simd_isa",
            "target": "vex_128_encoding",
            "type": "uses",
            "description": "Legacy SIMD ISA uses VEX.128 Encoding for promotion",
            "evidence_quote": "",
            "source_page": 360
          },
          {
            "source": "pmaddwd",
            "target": "vex_128_encoding",
            "type": "supported by",
            "description": "PMADDWD instruction is supported by VEX.128 Encoding",
            "evidence_quote": "",
            "source_page": 360
          },
          {
            "source": "pcmpeqb",
            "target": "vex_128_encoding",
            "type": "supported by",
            "description": "PCMPEQB instruction is supported by VEX.128 Encoding",
            "evidence_quote": "",
            "source_page": 360
          },
          {
            "source": "128_bit_intel_avx_instruction_enhancement",
            "target": "vpermilpd",
            "type": "Includes",
            "description": "Includes permute double precision floating-point instruction",
            "evidence_quote": "",
            "source_page": 362
          },
          {
            "source": "128_bit_intel_avx_instruction_enhancement",
            "target": "vpermilps",
            "type": "Includes",
            "description": "Includes permute single precision floating-point instruction",
            "evidence_quote": "",
            "source_page": 362
          },
          {
            "source": "128_bit_intel_avx_instruction_enhancement",
            "target": "vtestps",
            "type": "Includes",
            "description": "Includes test for packed single precision sign bits",
            "evidence_quote": "",
            "source_page": 362
          },
          {
            "source": "128_bit_intel_avx_instruction_enhancement",
            "target": "vtestpd",
            "type": "Includes",
            "description": "Includes test for packed double precision sign bits",
            "evidence_quote": "",
            "source_page": 362
          },
          {
            "source": "legacy_simd_non_arithmetic_isa",
            "target": "vex_128_encoding",
            "type": "Supports",
            "description": "Supports VEX-128 encoding (promoted instructions)",
            "evidence_quote": "",
            "source_page": 362
          },
          {
            "source": "128_bit_intel_avx_instruction_enhancement",
            "target": "legacy_simd_non_arithmetic_isa",
            "type": "Includes Promoted",
            "description": "Includes promoted legacy SIMD non-arithmetic ISA",
            "evidence_quote": "",
            "source_page": 362
          },
          {
            "source": "cpuid_01h_ecx_avx",
            "target": "intel_avx",
            "type": "Indicates Support",
            "description": "AVX flag indicates support for Intel AVX instructions",
            "evidence_quote": "",
            "source_page": 363
          },
          {
            "source": "supports_avx",
            "target": "osxsave_feature_flag",
            "type": "checks",
            "description": "Checks via CPUID to verify OS support",
            "evidence_quote": "",
            "source_page": 364
          },
          {
            "source": "supports_avx",
            "target": "avx_feature_flag",
            "type": "checks",
            "description": "Checks via CPUID to verify hardware support",
            "evidence_quote": "",
            "source_page": 364
          },
          {
            "source": "supports_avx",
            "target": "xgetbv",
            "type": "uses instruction",
            "description": "Uses to retrieve XCR0 register value",
            "evidence_quote": "",
            "source_page": 364
          },
          {
            "source": "supports_avx",
            "target": "ymm_state",
            "type": "checks support for",
            "description": "Verifies OS enablement of YMM state",
            "evidence_quote": "",
            "source_page": 364
          },
          {
            "source": "cpuid_01h_ecx_avx_28",
            "target": "avx_feature_flag",
            "type": "insufficient indicator for",
            "description": "Hardware flag alone doesn't confirm AVX support",
            "evidence_quote": "",
            "source_page": 364
          },
          {
            "source": "ymm_state",
            "target": "supports_avx",
            "type": "required for",
            "description": "OS-enabled YMM state required for AVX support",
            "evidence_quote": "",
            "source_page": 364
          },
          {
            "source": "vex_encoded_aes_ni_detection_sequence",
            "target": "intel_avx_application_support",
            "type": "Prerequisite",
            "description": "Detection requires AVX support check",
            "evidence_quote": "",
            "source_page": 365
          }
        ],
        "communities": [
          {
            "id": "community-4",
            "entity_ids": [
              "128_bit_vector_processing",
              "branch_handling",
              "cpuid_01h_ecx_avx",
              "cpuid_01h_ecx_osxsave",
              "intel_avx",
              "intra_register_manipulation",
              "non_unit_strided_fetching",
              "variable_blend_instructions",
              "vbroadcastss",
              "vex_encoded_instructions",
              "xrstor",
              "xsave"
            ],
            "summary": "This graph community centers on Intel AVX (Advanced Vector Extensions), a technology providing VEX-encoded data processing instructions for SIMD programming, operating on 256-bit YMM registers. It encompasses capabilities like 128-bit vector processing (handling 128-bit SIMD data with VEX-encoded primitives), non-unit-strided fetching (enabling broadcast/masked move), intra-register manipulation (permuting elements), and branch handling (via variable blend instructions with four-operand syntax). VEX-encoded instructions, a core component, enhance flexibility (e.g., for variable blend instructions) and underpin 128-bit processing. Feature flags include CPUID.01H:ECX.AVX (indicating AVX support) and CPUID.01H:ECX.OSXSAVE (a prerequisite for AVX, implying XSAVE/XRSTOR support for extended state management).",
            "key_relationships": [
              {
                "source": "intel_avx",
                "target": "vex_encoded_instructions",
                "type": "includes",
                "description": "employs VEX prefix encoding for data processing"
              },
              {
                "source": "intel_avx",
                "target": "128_bit_vector_processing",
                "type": "supports",
                "description": "via non-arithmetic primitives with VEX.128 encoding"
              },
              {
                "source": "128_bit_vector_processing",
                "target": "non_unit_strided_fetching",
                "type": "enables",
                "description": "via broadcast and masked move SIMD data fetching primitives"
              },
              {
                "source": "128_bit_vector_processing",
                "target": "intra_register_manipulation",
                "type": "enables",
                "description": "via permute primitives for 128-bit SIMD register data"
              },
              {
                "source": "branch_handling",
                "target": "variable_blend_instructions",
                "type": "employs",
                "description": "four-operand syntax for branch conditions"
              },
              {
                "source": "cpuid_01h_ecx_avx",
                "target": "intel_avx",
                "type": "Indicates Support",
                "description": "flag signals AVX instruction support"
              },
              {
                "source": "cpuid_01h_ecx_osxsave",
                "target": "xsave",
                "type": "Implies Support",
                "description": "OSXSAVE=1 implies XSAVE support for extended state saving"
              }
            ],
            "source_pages": [
              361,
              363
            ]
          },
          {
            "id": "community-3",
            "entity_ids": [
              "avx_feature_flag",
              "cpuid_01h_ecx_aes_25_flag",
              "cpuid_01h_ecx_avx_28",
              "cpuid_01h_ecx_xsave_26",
              "intel_avx_application_support",
              "osxsave_feature_flag",
              "supports_avx",
              "vaesdec_instruction",
              "vex_encoded_aes_ni_detection_sequence",
              "xcr0_register",
              "xgetbv",
              "xgetbv_instruction",
              "xmm_ymm_state_support",
              "ymm_state"
            ],
            "summary": "This graph community focuses on detecting hardware and software support for Intel AVX instructions and VEX-encoded AES-NI instructions. Key elements include detection functions (e.g., supports_AVX()), hardware/OS feature flags (e.g., AVX, OSXSAVE), registers (XCR0), instructions (XGETBV), and detection sequences (e.g., VEX-encoded AES-NI detection). It emphasizes checking both hardware capabilities (via CPUID flags) and OS support (via XCR0 register state) to confirm enablement of SIMD states (YMM/XMM) required for these instructions.",
            "key_relationships": [
              {
                "source": "supports_avx",
                "target": [
                  "osxsave_feature_flag",
                  "avx_feature_flag",
                  "xgetbv"
                ],
                "description": "Function checks OS (OSXSAVE) and hardware (AVX) flags, and uses XGETBV to retrieve XCR0 for YMM state verification"
              },
              {
                "source": "vex_encoded_aes_ni_detection_sequence",
                "target": [
                  "cpuid_01h_ecx_aes_25_flag",
                  "intel_avx_application_support",
                  "xgetbv_instruction"
                ],
                "description": "Detection sequence requires AES hardware flag, AVX application support, and uses XGETBV to check XCR0 state"
              },
              {
                "source": "xcr0_register",
                "target": [
                  "xmm_ymm_state_support"
                ],
                "description": "Register stores state enablement status, indicating OS support for XMM/YMM states via XGETBV retrieval"
              },
              {
                "source": "vaesdec_instruction",
                "target": [
                  "vex_encoded_aes_ni_detection_sequence"
                ],
                "description": "VEX-encoded AES-NI instruction requires the detection sequence to verify support"
              },
              {
                "source": [
                  "cpuid_01h_ecx_avx_28",
                  "cpuid_01h_ecx_xsave_26"
                ],
                "target": [
                  "avx_feature_flag",
                  "osxsave_feature_flag"
                ],
                "description": "Hardware CPUID flags alone are insufficient; OS support (via OSXSAVE/XCR0) is required for full AVX/XSAVE enablement"
              }
            ],
            "source_pages": [
              363,
              364,
              365
            ]
          }
        ],
        "explicit_paths": []
      },
      "answer": "The AVX programming model is distinguished by several broad capabilities:  \n- **VEX-encoded data processing instructions for SIMD programming** and operation on **256-bit YMM register state** [361, 363].  \n- **128-bit vector processing** via VEX-encoded primitives, supporting legacy SIMD ISA promotion [360, 361, 363].  \n- **Non-unit-strided fetching** (enabling broadcast and masked move for SIMD data) [361, 363].  \n- **Intra-register manipulation** (e.g., permute instructions like VPERMILPD, VPERMILPS) [362, 363].  \n- **Branch handling** via variable blend instructions with four-operand syntax [361, 363].  \n- Enhanced 128-bit AVX instructions including test operations (e.g., VTESTPD, VTESTPS) [362].",
      "query_latency_ms": 16544.904,
      "external_judge": {
        "id": "graphrag:concept_avx_features",
        "score": 4,
        "correct": true,
        "reason": "The answer correctly identifies the broad capabilities that distinguish the AVX programming model, including VEX-encoded data processing instructions, 128-bit vector processing, non-unit-strided fetching, intra-register manipulation, and branch handling. The answer is consistent with the information provided in the reference."
      }
    },
    {
      "id": "raptor:relation_avx_detection",
      "method": "raptor",
      "query_id": "relation_avx_detection",
      "category": "relationship-multi-hop",
      "question": "What complete processor-and-operating-system checks must an application perform before using AVX?",
      "reference": "Check CPUID OSXSAVE bit 27 and AVX bit 28, execute XGETBV with ECX=0, and verify XCR0 bits 2:1 are 11b so both XMM and YMM state are enabled by the OS.",
      "gold_pages": [
        363,
        364
      ],
      "retrieved_pages": [
        360,
        361,
        362,
        363,
        364,
        365
      ],
      "citation_recall": 1.0,
      "retrieval_trace": [
        {
          "id": "leaf-364",
          "level": 0,
          "summary": "Describes the recommended process for detecting Intel® AVX instructions, including pseudocode for a supports_AVX() function. The process involves using CPUID to check OSXSAVE and AVX feature flags in ECX; if set, XGETBV (with ECX=0) is used to verify the operating system has enabled XMM and YMM state support by checking EAX after AND with 06H. A note warns against relying exclusively on CPUID.01H:ECX.AVX[28] or XSAVE[26], as these indicate hardware support only, not operating system support; without OS-enabled YMM state management, Intel AVX instructions will cause #UD. These steps also apply to enhanced 128-bit SIMD floating-point instructions in Intel AVX (using VEX prefix-encoding) operating on YMM states.",
          "key_terms": [
            "Intel® AVX",
            "detection process",
            "pseudocode",
            "supports_AVX()",
            "CPUID",
            "OSXSAVE",
            "AVX feature flags",
            "ECX",
            "XGETBV",
            "XMM state",
            "YMM state",
            "OS support",
            "hardware support",
            "#UD",
            "enhanced 128-bit SIMD floating-point instructions",
            "VEX prefix-encoding"
          ],
          "source_pages": [
            364
          ],
          "children": [],
          "text_preview": "PROGRAMMING WITH INTEL® AVX, FMA, AND INTEL® AVX2\n\n\nThe following pseudocode illustrates this recommended application Intel AVX detection process:\n\nExample 14-1. Detection of Intel® AVX Instruction\n\nINT supports_AVX()\n{ mov        eax, 1\n   cpuid\n   and       ecx, 018000000H\n   cmp       ecx, 018000000H; check both OSXSAVE and AVX feature flags\n    jne      not_supported\n   ; processor supports AVX instructions and XGETBV is enabled by OS\n   mov       ecx, 0; specify 0 for XCR0 register\n   XGETBV              ; result in EDX:EAX\n   and       eax, 06H\n   cmp       eax, 06H; check OS has enabled both XMM and YMM state support\n   jne       not_supported\n   mov       eax, 1\n   jmp       done\nNOT_SUPPORTED:\n   mov       eax, 0\n   done:\n}\n\n\n                                                          NOTE\n         It is unwise for an application to rely exclusively on CPUID.01H:ECX.AVX[28] or at all on\n         CPUID.01H:ECX.XSAVE[26]: These indicate hardware support but not operating system support. If\n         YMM state management is not enabled by an operating systems, Intel AVX instructions will #UD\n         regardless of CPUID.01H:ECX.AVX[28]. “CPUID.01H:ECX.XSAVE[26] = 1” does not gua",
          "score": 0.6579365134239197
        },
        {
          "id": "leaf-365",
          "level": 0,
          "summary": "This section covers detection sequences for VEX-encoded AES instructions (e.g., VAESDEC, VAESDECLAST, VAESENC, VAESENCLAST, VAESIMC, VAESKEYGENASSIST) and VPCLMULQDQ instructions. Detection of VEX-encoded AES instructions requires checking CPUID.01H:ECX.AES[25] = 1 and application support for Intel AVX, as demonstrated in Example 14-2, which includes CPUID checks for OSXSAVE, AVX, and AESNI feature flags, and using XGETBV to verify OS-enabled XMM and YMM state support. Similarly, detection of VEX-encoded VPCLMULQDQ requires checking CPUID.01H:ECX.PCLMULQDQ[1] = 1 and AVX support, shown in Example 14-3 with CPUID checks for OSXSAVE, AVX, and PCLMULQDQ feature flags, and XGETBV to confirm OS-enabled XMM and YMM state support.",
          "key_terms": [
            "VEX-encoded AES",
            "VPCLMULQDQ",
            "VAESDEC",
            "VAESDECLAST",
            "VAESENC",
            "VAESENCLAST",
            "VAESIMC",
            "VAESKEYGENASSIST",
            "YMM states",
            "CPUID",
            "Intel AVX",
            "XGETBV",
            "XMM states",
            "AESNI feature flag",
            "PCLMULQDQ feature flag",
            "XCR0 register",
            "OSXSAVE"
          ],
          "source_pages": [
            365
          ],
          "children": [],
          "text_preview": "PROGRAMMING WITH INTEL® AVX, FMA, AND INTEL® AVX2\n\n\n\n14.3.1      Detection of VEX-Encoded AES and VPCLMULQDQ\nThe VAESDEC/VAESDECLAST/VAESENC/VAESENCLAST/VAESIMC/VAESKEYGENASSIST instructions operate on\nYMM states. The detection sequence must combine checking for CPUID.01H:ECX.AES[25] = 1 and the sequence\nfor detection application support for Intel AVX.\n\nExample 14-2. Detection of VEX-Encoded Intel® AES-NI Instructions\n\nINT supports_VAESNI()\n{ mov        eax, 1\n   cpuid\n   and       ecx, 01A000000H\n   cmp       ecx, 01A000000H; check OSXSAVE AVX and AESNI feature flags\n    jne      not_supported\n   ; processor supports AVX and VEX-encoded AESNI and XGETBV is enabled by OS\n   mov       ecx, 0; specify 0 for XCR0 register\n   XGETBV              ; result in EDX:EAX\n   and       eax, 06H\n   cmp       eax, 06H; check OS has enabled both XMM and YMM state support\n   jne       not_supported\n   mov       eax, 1\n   jmp       done\nNOT_SUPPORTED:\n   mov       eax, 0\ndone:\n\n\nSimilarly, the detection sequence for VPCLMULQDQ must combine checking for CPUID.01H:ECX.PCLMULQDQ[1] =\n1 and the sequence for detection application support for Intel AVX.\nThis is shown in the pseudocode provided in Example",
          "score": 0.5803934335708618
        },
        {
          "id": "leaf-363",
          "level": 0,
          "summary": "The content includes a continuation of Table 14-7, which lists Legacy SIMD ISA instructions (e.g., PBLENDVB, PBLENDW, PEXTRW/B/D/Q, PINSRB/D/Q) promoted to 128-bit non-arithmetic Intel AVX instructions (VEX.256 encoding: no, VEX.128 encoding: yes) with 'VI' (Vector Integer) as the reason for not being promoted to 256-bit. Section 14.3 covers detection of Intel AVX instructions, requiring checks for OS support (CPUID.01H:ECX.OSXSAVE[27] = 1, XGETBV verifying XCR0[2:1] = '11b' for XMM/YMM state enable) and processor support (CPUID.01H:ECX.AVX[28] = 1), with a recommended sequence involving these steps.",
          "key_terms": [
            "Legacy SIMD ISA",
            "Intel AVX",
            "VEX.256 Encoding",
            "VEX.128 Encoding",
            "PBLENDVB",
            "PBLENDW",
            "PEXTRW",
            "PEXTRB",
            "PEXTRD",
            "PEXTRQ",
            "PINSRB",
            "PINSRD",
            "PINSRQ",
            "VI (Vector Integer)",
            "YMM register state",
            "XGETBV instruction",
            "XSAVE/XRSTOR",
            "CPUID.01H:ECX.OSXSAVE[27]",
            "XCR0[2:1] = '11b'",
            "CPUID.01H:ECX.AVX[28]"
          ],
          "source_pages": [
            363
          ],
          "children": [],
          "text_preview": "PROGRAMMING WITH INTEL® AVX, FMA, AND INTEL® AVX2\n\n\n       Table 14-7. Promotion of Legacy SIMD ISA to 128-Bit Non-Arithmetic Intel® AVX instruction (Contd.)\n     VEX.256            VEX.128\n                                                                Instruction                              Reason Not Promoted\n     Encoding           Encoding\n\nno                yes                  PBLENDVB, PBLENDW                                            VI\nno                yes                  PEXTRW, PEXTRB, PEXTRD, PEXTRQ                               VI\nno                yes                  PINSRB, PINSRD, PINSRQ                                       VI\n\nDescription of column “Reason not promoted”:\n•    MMX: Instructions referencing MMX registers do not support VEX.\n•    Scalar: Scalar instructions are not promoted to 256-bit.\n•    VI: “Vector Integer” instructions are not promoted to 256-bit.\n•    Note 1: MOVLPD/PS and MOVHPD/PS are not promoted to 256-bit. The equivalent functionality are provided\n     by VINSERTF128 and VEXTRACTF128 instructions as the existing instructions have no natural 256b extension\n•    Note 3: It is expected that using 128-bit INSERTPS followed by a VINSERTF1",
          "score": 0.5324614644050598
        },
        {
          "id": "parent-1",
          "level": 1,
          "summary": "Pages 360-365 detail the promotion of Legacy SIMD ISA to 128-bit Intel AVX instructions (arithmetic and non-arithmetic), 128-bit non-arithmetic AVX enhancements, and detection processes for AVX, VEX-encoded AES, and VPCLMULQDQ. Table 14-5 covers 128-bit arithmetic promotion: most have VEX.128 (yes) and VEX.256 (no), with reasons like 'VI' (Vector Integer), 'Scalar', or 'Integer'; includes AES instructions (e.g., AESDEC) with 'VI' as 256-bit promotion reason. 128-bit non-arithmetic AVX primitives (Table 14-6) offer same functionality as SIMD prefix-encoded XMM instructions plus enhancements (broadcast, masked move, permute, branch handling like variable blend or packed TEST for floating-point). Table 14-7 details remaining non-arithmetic promotion: instructions (e.g., PBLENDVB, PEXTRW) have VEX.128 (yes), VEX.256 (no), with reasons like 'VI', 'MMX', or 'redundant'. Legacy non-arithmetic ISA promoted to VEX-256 also support VEX-128 (Table 14-3). AVX detection requires CPU support (CPUID.01H:ECX.AVX[28] = 1) and OS support (CPUID.01H:ECX.OSXSAVE[27] = 1, XGETBV verifying XCR0[2:1] = '11b'). VEX-encoded AES and VPCLMULQDQ detection build on AVX detection, requiring their specific CPUID flags (AESNI[25] for AES, PCLMULQDQ[1] for VPCLMULQDQ) plus OS-enabled XMM/YMM state via XGETBV.",
          "key_relationships": {
            "Tables": "Table 14-5 (arithmetic promotion), Table 14-6 (128-bit non-arithmetic enhancements), Table 14-7 (remaining non-arithmetic promotion) are core; Table 14-3 notes VEX-256 promoted non-arithmetic ISA also support VEX-128.",
            "Promotion Reasons": "'VI' (Vector Integer) is a common reason for 256-bit non-promotion across arithmetic (Table 14-5) and non-arithmetic (Table 14-7) instructions.",
            "AVX Detection": "Requires both CPU support (CPUID.01H:ECX.AVX[28]) and OS support (OSXSAVE flag + XGETBV XCR0[2:1] = '11b') to avoid #UD.",
            "AES/VPCLMULQDQ Detection": "Build on AVX detection, adding their specific CPUID flags (AESNI[25] for AES, PCLMULQDQ[1] for VPCLMULQDQ) while retaining OS support checks via XGETBV."
          },
          "source_pages": [
            360,
            361,
            362,
            363,
            364,
            365
          ],
          "children": [
            "leaf-360",
            "leaf-361",
            "leaf-362",
            "leaf-363",
            "leaf-364",
            "leaf-365"
          ],
          "score": 0.5245624780654907
        },
        {
          "id": "leaf-360",
          "level": 0,
          "summary": "This page continues Table 14-5, which details the promotion of Legacy SIMD ISA to 128-bit Arithmetic Intel® AVX Instructions. The table includes columns for VEX.256 Encoding (mostly 'no'), VEX.128 Encoding (mostly 'yes'), specific instructions, and reasons for not being promoted (e.g., 'VI', 'Scalar', 'Integer'). Relevant CPUID flags are also noted (e.g., CPUID.01H:ECX.SSSE3[9], SSE4_1[19], POPCNT[23], SSE4_2[20], PCLMULQDQ[1], AESNI[25]).",
          "key_terms": [
            "Legacy SIMD ISA",
            "128-Bit Arithmetic Intel® AVX Instructions",
            "VEX.256 Encoding",
            "VEX.128 Encoding",
            "Table 14-5",
            "CPUID.01H:ECX.SSSE3[9]",
            "CPUID.01H:ECX.SSE4_1[19]",
            "CPUID.01H:ECX.POPCNT[23]",
            "CPUID.01H:ECX.SSE4_2[20]",
            "CPUID.01H:ECX.PCLMULQDQ[1]",
            "CPUID.01H:ECX.AESNI[25]",
            "VI",
            "Scalar",
            "Integer",
            "PMADDWD",
            "PMADDUBSW",
            "PAVGB",
            "PAVGW",
            "PMULUDQ",
            "PCMPEQB",
            "PCMPEQW",
            "PCMPEQD",
            "PMULLW",
            "PMULHUW",
            "PMULHW",
            "PSUBSW",
            "PADDSW",
            "PSADBW",
            "PADDUSB",
            "PADDUSW",
            "PADDSB",
            "PSUBUSB",
            "PSUBUSW",
            "PSUBSB",
            "PMINUB",
            "PMINSW",
            "PMAXUB",
            "PMAXSW",
            "PADDB",
            "PADDW",
            "PADDD",
            "PADDQ",
            "PSUBB",
            "PSUBW",
            "PSUBD",
            "PSUBQ",
            "PSLLW",
            "PSLLD",
            "PSLLQ",
            "PSRAW",
            "PSRLW",
            "PSRLD",
            "PSRLQ",
            "PSRAD",
            "PHSUBW",
            "PHSUBD",
            "PHSUBSW",
            "PHADDW",
            "PHADDD",
            "PHADDSW",
            "PMULHRSW",
            "PSIGNB",
            "PSIGNW",
            "PSIGND",
            "PABSB",
            "PABSW",
            "PABSD",
            "DPPD",
            "PHMINPOSUW",
            "MPSADBW",
            "PMAXSB",
            "PMAXSD",
            "PMAXUD",
            "PMINSB",
            "PMINSD",
            "PMINUD",
            "PMAXUW",
            "PMINUW",
            "PMOVSXxx",
            "PMOVZXxx",
            "PMULDQ",
            "PMULLD",
            "ROUNDSD",
            "ROUNDSS",
            "POPCNT",
            "PCMPGTQ",
            "CRC32",
            "PCMPESTRI",
            "PCMPESTRM",
            "PCMPISTRI",
            "PCMPISTRM",
            "PCLMULQDQ"
          ],
          "source_pages": [
            360
          ],
          "children": [],
          "text_preview": "PROGRAMMING WITH INTEL® AVX, FMA, AND INTEL® AVX2\n\n\n          Table 14-5. Promotion of Legacy SIMD ISA to 128-Bit Arithmetic Intel® AVX Instructions (Contd.)\n      VEX.256           VEX.128\n                                                          Instruction                      Reason Not Promoted\n      Encoding          Encoding\n no               yes              PMADDWD, PMADDUBSW                                 VI\n no               yes              PAVGB, PAVGW, PMULUDQ                              VI\n no               yes              PCMPEQB, PCMPEQW, PCMPEQD                          VI\n no               yes              PMULLW, PMULHUW, PMULHW                            VI\n no               yes              PSUBSW, PADDSW, PSADBW                             VI\n no               yes              PADDUSB, PADDUSW, PADDSB                           VI\n no               yes              PSUBUSB, PSUBUSW, PSUBSB                           VI\n no               yes              PMINUB, PMINSW                                     VI\n no               yes              PMAXUB, PMAXSW                                     VI\n no               yes              PADDB, PADDW, PADDD, PADDQ    ",
          "score": 0.429201602935791
        }
      ],
      "answer": "To use AVX, an application must perform the following processor and operating system checks:  \n\n### **Processor Support Check**:  \nVerify the CPU supports AVX by checking the AVX feature flag in CPUID.01H:ECX. Specifically, ensure CPUID.01H:ECX.AVX[bit 28] = 1 [363, 364, 360-365].  \n\n### **Operating System Support Checks**:  \n1. **OSXSAVE Flag Check**: Confirm the OS supports XSAVE/XRSTOR by checking CPUID.01H:ECX.OSXSAVE[bit 27] = 1 [363, 364, 360-365].  \n2. **XMM/YMM State Enable Check**: Use the XGETBV instruction (with ECX=0) to verify the OS has enabled XMM and YMM state management. Check that the result in EAX, after AND with 06H, equals 06H (i.e., XCR0[2:1] = '11b') [363, 364, 360-365].  \n\n**Note**: Relying exclusively on CPUID.01H:ECX.AVX[28] or XSAVE[26] is insufficient, as these only indicate hardware support, not OS-enabled YMM state management (without which AVX instructions cause #UD) [364].",
      "query_latency_ms": 17659.241,
      "external_judge": {
        "id": "raptor:relation_avx_detection",
        "score": 4,
        "correct": true,
        "reason": "The answer correctly outlines the complete processor-and-operating-system checks that must be performed before using AVX, including checking the OSXSAVE and AVX bits in CPUID, executing XGETBV to verify XCR0 bits, and ensuring both XMM and YMM state are enabled by the OS. The answer is detailed and aligns with the provided reference."
      }
    },
    {
      "id": "graphrag:relation_avx_detection",
      "method": "graphrag",
      "query_id": "relation_avx_detection",
      "category": "relationship-multi-hop",
      "question": "What complete processor-and-operating-system checks must an application perform before using AVX?",
      "reference": "Check CPUID OSXSAVE bit 27 and AVX bit 28, execute XGETBV with ECX=0, and verify XCR0 bits 2:1 are 11b so both XMM and YMM state are enabled by the OS.",
      "gold_pages": [
        363,
        364
      ],
      "retrieved_pages": [
        361,
        362,
        363,
        364,
        365
      ],
      "citation_recall": 1.0,
      "retrieval_trace": {
        "entities": [
          {
            "id": "128_bit_intel_avx_instruction_enhancement",
            "name": "128-bit Intel® AVX Instruction Enhancement",
            "type": "Instruction Set",
            "descriptions": [
              "Enhanced 128-bit AVX instructions including permute and test"
            ],
            "evidence": [],
            "source_pages": [
              362
            ]
          },
          {
            "id": "avx_feature_flag",
            "name": "AVX feature flag",
            "type": "Feature Flag",
            "descriptions": [
              "Indicates hardware support for AVX instructions"
            ],
            "evidence": [],
            "source_pages": [
              364
            ]
          },
          {
            "id": "cpuid_01h_ecx_aes_25_flag",
            "name": "CPUID.01H:ECX.AES[25] flag",
            "type": "CPUID Flag",
            "descriptions": [
              "Prerequisite flag for VEX-encoded AES-NI instruction detection"
            ],
            "evidence": [],
            "source_pages": [
              365
            ]
          },
          {
            "id": "cpuid_01h_ecx_avx",
            "name": "CPUID.01H:ECX.AVX",
            "type": "Feature Flag",
            "descriptions": [
              "CPUID flag indicating AVX instruction support"
            ],
            "evidence": [],
            "source_pages": [
              363
            ]
          },
          {
            "id": "cpuid_01h_ecx_avx_28",
            "name": "CPUID.01H:ECX.AVX[28]",
            "type": "CPUID Feature Flag",
            "descriptions": [
              "Hardware support indicator for Intel AVX"
            ],
            "evidence": [],
            "source_pages": [
              364
            ]
          },
          {
            "id": "intel_avx",
            "name": "Intel AVX",
            "type": "Technology",
            "descriptions": [
              "Provides VEX-encoded data processing instructions for SIMD programming",
              "Instruction set operating on 256-bit YMM register state"
            ],
            "evidence": [],
            "source_pages": [
              361,
              363
            ]
          },
          {
            "id": "intel_avx_application_support",
            "name": "Intel AVX application support",
            "type": "concept",
            "descriptions": [],
            "evidence": [],
            "source_pages": [
              365
            ]
          },
          {
            "id": "legacy_simd_non_arithmetic_isa",
            "name": "Legacy SIMD non-arithmetic ISA",
            "type": "ISA Component",
            "descriptions": [
              "Legacy SIMD instructions without arithmetic operations"
            ],
            "evidence": [],
            "source_pages": [
              362
            ]
          },
          {
            "id": "osxsave_feature_flag",
            "name": "OSXSAVE feature flag",
            "type": "Feature Flag",
            "descriptions": [
              "Indicates OS support for XSAVE functionality"
            ],
            "evidence": [],
            "source_pages": [
              364
            ]
          },
          {
            "id": "supports_avx",
            "name": "supports_AVX()",
            "type": "Function",
            "descriptions": [
              "Function to detect Intel AVX instruction support"
            ],
            "evidence": [],
            "source_pages": [
              364
            ]
          },
          {
            "id": "vaesdec_instruction",
            "name": "VAESDEC instruction",
            "type": "Instruction",
            "descriptions": [
              "Operates on YMM states; part of VEX-encoded AES-NI instructions"
            ],
            "evidence": [],
            "source_pages": [
              365
            ]
          },
          {
            "id": "vex_encoded_aes_ni_detection_sequence",
            "name": "VEX-encoded AES-NI detection sequence",
            "type": "Detection Sequence",
            "descriptions": [
              "Combines AES flag check and Intel AVX application support check"
            ],
            "evidence": [],
            "source_pages": [
              365
            ]
          },
          {
            "id": "vpermilpd",
            "name": "VPERMILPD",
            "type": "Instruction",
            "descriptions": [
              "Permute double precision floating-point values with controls"
            ],
            "evidence": [],
            "source_pages": [
              362
            ]
          },
          {
            "id": "vpermilps",
            "name": "VPERMILPS",
            "type": "Instruction",
            "descriptions": [
              "Permute single precision floating-point values with controls"
            ],
            "evidence": [],
            "source_pages": [
              362
            ]
          },
          {
            "id": "vtestpd",
            "name": "VTESTPD",
            "type": "Instruction",
            "descriptions": [
              "Set ZF/CF based on packed double precision sign bits"
            ],
            "evidence": [],
            "source_pages": [
              362
            ]
          },
          {
            "id": "vtestps",
            "name": "VTESTPS",
            "type": "Instruction",
            "descriptions": [
              "Set ZF/CF based on packed single precision sign bits"
            ],
            "evidence": [],
            "source_pages": [
              362
            ]
          },
          {
            "id": "xgetbv",
            "name": "XGETBV",
            "type": "Instruction",
            "descriptions": [
              "Instruction to check enabled state in XCR0",
              "Instruction to retrieve XCR0 register value"
            ],
            "evidence": [],
            "source_pages": [
              363,
              364
            ]
          },
          {
            "id": "xgetbv_instruction",
            "name": "XGETBV instruction",
            "type": "Instruction",
            "descriptions": [
              "Retrieves XCR0 value to check OS-enabled XMM/YMM support"
            ],
            "evidence": [],
            "source_pages": [
              365
            ]
          },
          {
            "id": "ymm_state",
            "name": "YMM state",
            "type": "CPU State",
            "descriptions": [
              "SIMD state used by Intel AVX instructions"
            ],
            "evidence": [],
            "source_pages": [
              364
            ]
          }
        ],
        "relationships": [
          {
            "source": "128_bit_intel_avx_instruction_enhancement",
            "target": "vpermilpd",
            "type": "Includes",
            "description": "Includes permute double precision floating-point instruction",
            "evidence_quote": "",
            "source_page": 362
          },
          {
            "source": "128_bit_intel_avx_instruction_enhancement",
            "target": "vpermilps",
            "type": "Includes",
            "description": "Includes permute single precision floating-point instruction",
            "evidence_quote": "",
            "source_page": 362
          },
          {
            "source": "128_bit_intel_avx_instruction_enhancement",
            "target": "vtestps",
            "type": "Includes",
            "description": "Includes test for packed single precision sign bits",
            "evidence_quote": "",
            "source_page": 362
          },
          {
            "source": "128_bit_intel_avx_instruction_enhancement",
            "target": "vtestpd",
            "type": "Includes",
            "description": "Includes test for packed double precision sign bits",
            "evidence_quote": "",
            "source_page": 362
          },
          {
            "source": "128_bit_intel_avx_instruction_enhancement",
            "target": "legacy_simd_non_arithmetic_isa",
            "type": "Includes Promoted",
            "description": "Includes promoted legacy SIMD non-arithmetic ISA",
            "evidence_quote": "",
            "source_page": 362
          },
          {
            "source": "cpuid_01h_ecx_avx",
            "target": "intel_avx",
            "type": "Indicates Support",
            "description": "AVX flag indicates support for Intel AVX instructions",
            "evidence_quote": "",
            "source_page": 363
          },
          {
            "source": "supports_avx",
            "target": "osxsave_feature_flag",
            "type": "checks",
            "description": "Checks via CPUID to verify OS support",
            "evidence_quote": "",
            "source_page": 364
          },
          {
            "source": "supports_avx",
            "target": "avx_feature_flag",
            "type": "checks",
            "description": "Checks via CPUID to verify hardware support",
            "evidence_quote": "",
            "source_page": 364
          },
          {
            "source": "supports_avx",
            "target": "xgetbv",
            "type": "uses instruction",
            "description": "Uses to retrieve XCR0 register value",
            "evidence_quote": "",
            "source_page": 364
          },
          {
            "source": "supports_avx",
            "target": "ymm_state",
            "type": "checks support for",
            "description": "Verifies OS enablement of YMM state",
            "evidence_quote": "",
            "source_page": 364
          },
          {
            "source": "cpuid_01h_ecx_avx_28",
            "target": "avx_feature_flag",
            "type": "insufficient indicator for",
            "description": "Hardware flag alone doesn't confirm AVX support",
            "evidence_quote": "",
            "source_page": 364
          },
          {
            "source": "ymm_state",
            "target": "supports_avx",
            "type": "required for",
            "description": "OS-enabled YMM state required for AVX support",
            "evidence_quote": "",
            "source_page": 364
          },
          {
            "source": "vaesdec_instruction",
            "target": "vex_encoded_aes_ni_detection_sequence",
            "type": "Requires",
            "description": "VAESDEC requires detection sequence to verify support",
            "evidence_quote": "",
            "source_page": 365
          },
          {
            "source": "vex_encoded_aes_ni_detection_sequence",
            "target": "cpuid_01h_ecx_aes_25_flag",
            "type": "Prerequisite",
            "description": "Detection sequence checks AES[25] flag for support",
            "evidence_quote": "",
            "source_page": 365
          },
          {
            "source": "vex_encoded_aes_ni_detection_sequence",
            "target": "intel_avx_application_support",
            "type": "Prerequisite",
            "description": "Detection requires AVX support check",
            "evidence_quote": "",
            "source_page": 365
          },
          {
            "source": "vex_encoded_aes_ni_detection_sequence",
            "target": "xgetbv_instruction",
            "type": "Uses",
            "description": "Detection uses XGETBV to check XCR0 state",
            "evidence_quote": "",
            "source_page": 365
          }
        ],
        "communities": [
          {
            "id": "community-3",
            "entity_ids": [
              "avx_feature_flag",
              "cpuid_01h_ecx_aes_25_flag",
              "cpuid_01h_ecx_avx_28",
              "cpuid_01h_ecx_xsave_26",
              "intel_avx_application_support",
              "osxsave_feature_flag",
              "supports_avx",
              "vaesdec_instruction",
              "vex_encoded_aes_ni_detection_sequence",
              "xcr0_register",
              "xgetbv",
              "xgetbv_instruction",
              "xmm_ymm_state_support",
              "ymm_state"
            ],
            "summary": "This graph community focuses on detecting hardware and software support for Intel AVX instructions and VEX-encoded AES-NI instructions. Key elements include detection functions (e.g., supports_AVX()), hardware/OS feature flags (e.g., AVX, OSXSAVE), registers (XCR0), instructions (XGETBV), and detection sequences (e.g., VEX-encoded AES-NI detection). It emphasizes checking both hardware capabilities (via CPUID flags) and OS support (via XCR0 register state) to confirm enablement of SIMD states (YMM/XMM) required for these instructions.",
            "key_relationships": [
              {
                "source": "supports_avx",
                "target": [
                  "osxsave_feature_flag",
                  "avx_feature_flag",
                  "xgetbv"
                ],
                "description": "Function checks OS (OSXSAVE) and hardware (AVX) flags, and uses XGETBV to retrieve XCR0 for YMM state verification"
              },
              {
                "source": "vex_encoded_aes_ni_detection_sequence",
                "target": [
                  "cpuid_01h_ecx_aes_25_flag",
                  "intel_avx_application_support",
                  "xgetbv_instruction"
                ],
                "description": "Detection sequence requires AES hardware flag, AVX application support, and uses XGETBV to check XCR0 state"
              },
              {
                "source": "xcr0_register",
                "target": [
                  "xmm_ymm_state_support"
                ],
                "description": "Register stores state enablement status, indicating OS support for XMM/YMM states via XGETBV retrieval"
              },
              {
                "source": "vaesdec_instruction",
                "target": [
                  "vex_encoded_aes_ni_detection_sequence"
                ],
                "description": "VEX-encoded AES-NI instruction requires the detection sequence to verify support"
              },
              {
                "source": [
                  "cpuid_01h_ecx_avx_28",
                  "cpuid_01h_ecx_xsave_26"
                ],
                "target": [
                  "avx_feature_flag",
                  "osxsave_feature_flag"
                ],
                "description": "Hardware CPUID flags alone are insufficient; OS support (via OSXSAVE/XCR0) is required for full AVX/XSAVE enablement"
              }
            ],
            "source_pages": [
              363,
              364,
              365
            ]
          },
          {
            "id": "community-4",
            "entity_ids": [
              "128_bit_vector_processing",
              "branch_handling",
              "cpuid_01h_ecx_avx",
              "cpuid_01h_ecx_osxsave",
              "intel_avx",
              "intra_register_manipulation",
              "non_unit_strided_fetching",
              "variable_blend_instructions",
              "vbroadcastss",
              "vex_encoded_instructions",
              "xrstor",
              "xsave"
            ],
            "summary": "This graph community centers on Intel AVX (Advanced Vector Extensions), a technology providing VEX-encoded data processing instructions for SIMD programming, operating on 256-bit YMM registers. It encompasses capabilities like 128-bit vector processing (handling 128-bit SIMD data with VEX-encoded primitives), non-unit-strided fetching (enabling broadcast/masked move), intra-register manipulation (permuting elements), and branch handling (via variable blend instructions with four-operand syntax). VEX-encoded instructions, a core component, enhance flexibility (e.g., for variable blend instructions) and underpin 128-bit processing. Feature flags include CPUID.01H:ECX.AVX (indicating AVX support) and CPUID.01H:ECX.OSXSAVE (a prerequisite for AVX, implying XSAVE/XRSTOR support for extended state management).",
            "key_relationships": [
              {
                "source": "intel_avx",
                "target": "vex_encoded_instructions",
                "type": "includes",
                "description": "employs VEX prefix encoding for data processing"
              },
              {
                "source": "intel_avx",
                "target": "128_bit_vector_processing",
                "type": "supports",
                "description": "via non-arithmetic primitives with VEX.128 encoding"
              },
              {
                "source": "128_bit_vector_processing",
                "target": "non_unit_strided_fetching",
                "type": "enables",
                "description": "via broadcast and masked move SIMD data fetching primitives"
              },
              {
                "source": "128_bit_vector_processing",
                "target": "intra_register_manipulation",
                "type": "enables",
                "description": "via permute primitives for 128-bit SIMD register data"
              },
              {
                "source": "branch_handling",
                "target": "variable_blend_instructions",
                "type": "employs",
                "description": "four-operand syntax for branch conditions"
              },
              {
                "source": "cpuid_01h_ecx_avx",
                "target": "intel_avx",
                "type": "Indicates Support",
                "description": "flag signals AVX instruction support"
              },
              {
                "source": "cpuid_01h_ecx_osxsave",
                "target": "xsave",
                "type": "Implies Support",
                "description": "OSXSAVE=1 implies XSAVE support for extended state saving"
              }
            ],
            "source_pages": [
              361,
              363
            ]
          }
        ],
        "explicit_paths": []
      },
      "answer": "To use AVX, an application must perform the following processor and operating system checks, based on the retrieved evidence:  \n\n1. **Check hardware support for AVX via the AVX feature flag**: Verify the AVX feature flag (e.g., CPUID.01H:ECX.AVX) to confirm the processor supports AVX instructions [363, 364].  \n\n2. **Check OS support for XSAVE functionality via the OSXSAVE feature flag**: Ensure the OSXSAVE feature flag is set, indicating the operating system supports XSAVE (required for managing extended register states like YMM) [364].  \n\n3. **Verify OS enablement of YMM state using the XGETBV instruction**: Use the XGETBV instruction to retrieve the XCR0 register and confirm the YMM state is enabled by the OS [364].  \n\nThese checks are collectively performed by the `supports_AVX()` function, which validates hardware (AVX flag), OS (OSXSAVE flag), and YMM state enablement (via XCR0) [364].  \n\nEvidence is sufficient for these checks.",
      "query_latency_ms": 14202.464,
      "external_judge": {
        "id": "graphrag:relation_avx_detection",
        "score": 4,
        "correct": true,
        "reason": "The answer correctly identifies the processor and operating system checks required before using AVX, including checking the AVX feature flag, OSXSAVE feature flag, and verifying OS enablement of YMM state using the XGETBV instruction. The answer is consistent with the information provided in the reference."
      }
    },
    {
      "id": "raptor:relation_cpuid_insufficient",
      "method": "raptor",
      "query_id": "relation_cpuid_insufficient",
      "category": "relationship-multi-hop",
      "question": "Why is CPUID.AVX alone insufficient proof that AVX instructions can execute?",
      "reference": "The operating system must enable XSAVE/XGETBV and XMM/YMM state management in XCR0; otherwise AVX instructions raise #UD even when CPUID.AVX is set.",
      "gold_pages": [
        323,
        363,
        364
      ],
      "retrieved_pages": [
        360,
        361,
        362,
        363,
        364,
        365
      ],
      "citation_recall": 0.6666666666666666,
      "retrieval_trace": [
        {
          "id": "leaf-364",
          "level": 0,
          "summary": "Describes the recommended process for detecting Intel® AVX instructions, including pseudocode for a supports_AVX() function. The process involves using CPUID to check OSXSAVE and AVX feature flags in ECX; if set, XGETBV (with ECX=0) is used to verify the operating system has enabled XMM and YMM state support by checking EAX after AND with 06H. A note warns against relying exclusively on CPUID.01H:ECX.AVX[28] or XSAVE[26], as these indicate hardware support only, not operating system support; without OS-enabled YMM state management, Intel AVX instructions will cause #UD. These steps also apply to enhanced 128-bit SIMD floating-point instructions in Intel AVX (using VEX prefix-encoding) operating on YMM states.",
          "key_terms": [
            "Intel® AVX",
            "detection process",
            "pseudocode",
            "supports_AVX()",
            "CPUID",
            "OSXSAVE",
            "AVX feature flags",
            "ECX",
            "XGETBV",
            "XMM state",
            "YMM state",
            "OS support",
            "hardware support",
            "#UD",
            "enhanced 128-bit SIMD floating-point instructions",
            "VEX prefix-encoding"
          ],
          "source_pages": [
            364
          ],
          "children": [],
          "text_preview": "PROGRAMMING WITH INTEL® AVX, FMA, AND INTEL® AVX2\n\n\nThe following pseudocode illustrates this recommended application Intel AVX detection process:\n\nExample 14-1. Detection of Intel® AVX Instruction\n\nINT supports_AVX()\n{ mov        eax, 1\n   cpuid\n   and       ecx, 018000000H\n   cmp       ecx, 018000000H; check both OSXSAVE and AVX feature flags\n    jne      not_supported\n   ; processor supports AVX instructions and XGETBV is enabled by OS\n   mov       ecx, 0; specify 0 for XCR0 register\n   XGETBV              ; result in EDX:EAX\n   and       eax, 06H\n   cmp       eax, 06H; check OS has enabled both XMM and YMM state support\n   jne       not_supported\n   mov       eax, 1\n   jmp       done\nNOT_SUPPORTED:\n   mov       eax, 0\n   done:\n}\n\n\n                                                          NOTE\n         It is unwise for an application to rely exclusively on CPUID.01H:ECX.AVX[28] or at all on\n         CPUID.01H:ECX.XSAVE[26]: These indicate hardware support but not operating system support. If\n         YMM state management is not enabled by an operating systems, Intel AVX instructions will #UD\n         regardless of CPUID.01H:ECX.AVX[28]. “CPUID.01H:ECX.XSAVE[26] = 1” does not gua",
          "score": 0.6636016964912415
        },
        {
          "id": "leaf-363",
          "level": 0,
          "summary": "The content includes a continuation of Table 14-7, which lists Legacy SIMD ISA instructions (e.g., PBLENDVB, PBLENDW, PEXTRW/B/D/Q, PINSRB/D/Q) promoted to 128-bit non-arithmetic Intel AVX instructions (VEX.256 encoding: no, VEX.128 encoding: yes) with 'VI' (Vector Integer) as the reason for not being promoted to 256-bit. Section 14.3 covers detection of Intel AVX instructions, requiring checks for OS support (CPUID.01H:ECX.OSXSAVE[27] = 1, XGETBV verifying XCR0[2:1] = '11b' for XMM/YMM state enable) and processor support (CPUID.01H:ECX.AVX[28] = 1), with a recommended sequence involving these steps.",
          "key_terms": [
            "Legacy SIMD ISA",
            "Intel AVX",
            "VEX.256 Encoding",
            "VEX.128 Encoding",
            "PBLENDVB",
            "PBLENDW",
            "PEXTRW",
            "PEXTRB",
            "PEXTRD",
            "PEXTRQ",
            "PINSRB",
            "PINSRD",
            "PINSRQ",
            "VI (Vector Integer)",
            "YMM register state",
            "XGETBV instruction",
            "XSAVE/XRSTOR",
            "CPUID.01H:ECX.OSXSAVE[27]",
            "XCR0[2:1] = '11b'",
            "CPUID.01H:ECX.AVX[28]"
          ],
          "source_pages": [
            363
          ],
          "children": [],
          "text_preview": "PROGRAMMING WITH INTEL® AVX, FMA, AND INTEL® AVX2\n\n\n       Table 14-7. Promotion of Legacy SIMD ISA to 128-Bit Non-Arithmetic Intel® AVX instruction (Contd.)\n     VEX.256            VEX.128\n                                                                Instruction                              Reason Not Promoted\n     Encoding           Encoding\n\nno                yes                  PBLENDVB, PBLENDW                                            VI\nno                yes                  PEXTRW, PEXTRB, PEXTRD, PEXTRQ                               VI\nno                yes                  PINSRB, PINSRD, PINSRQ                                       VI\n\nDescription of column “Reason not promoted”:\n•    MMX: Instructions referencing MMX registers do not support VEX.\n•    Scalar: Scalar instructions are not promoted to 256-bit.\n•    VI: “Vector Integer” instructions are not promoted to 256-bit.\n•    Note 1: MOVLPD/PS and MOVHPD/PS are not promoted to 256-bit. The equivalent functionality are provided\n     by VINSERTF128 and VEXTRACTF128 instructions as the existing instructions have no natural 256b extension\n•    Note 3: It is expected that using 128-bit INSERTPS followed by a VINSERTF1",
          "score": 0.6427825093269348
        },
        {
          "id": "leaf-360",
          "level": 0,
          "summary": "This page continues Table 14-5, which details the promotion of Legacy SIMD ISA to 128-bit Arithmetic Intel® AVX Instructions. The table includes columns for VEX.256 Encoding (mostly 'no'), VEX.128 Encoding (mostly 'yes'), specific instructions, and reasons for not being promoted (e.g., 'VI', 'Scalar', 'Integer'). Relevant CPUID flags are also noted (e.g., CPUID.01H:ECX.SSSE3[9], SSE4_1[19], POPCNT[23], SSE4_2[20], PCLMULQDQ[1], AESNI[25]).",
          "key_terms": [
            "Legacy SIMD ISA",
            "128-Bit Arithmetic Intel® AVX Instructions",
            "VEX.256 Encoding",
            "VEX.128 Encoding",
            "Table 14-5",
            "CPUID.01H:ECX.SSSE3[9]",
            "CPUID.01H:ECX.SSE4_1[19]",
            "CPUID.01H:ECX.POPCNT[23]",
            "CPUID.01H:ECX.SSE4_2[20]",
            "CPUID.01H:ECX.PCLMULQDQ[1]",
            "CPUID.01H:ECX.AESNI[25]",
            "VI",
            "Scalar",
            "Integer",
            "PMADDWD",
            "PMADDUBSW",
            "PAVGB",
            "PAVGW",
            "PMULUDQ",
            "PCMPEQB",
            "PCMPEQW",
            "PCMPEQD",
            "PMULLW",
            "PMULHUW",
            "PMULHW",
            "PSUBSW",
            "PADDSW",
            "PSADBW",
            "PADDUSB",
            "PADDUSW",
            "PADDSB",
            "PSUBUSB",
            "PSUBUSW",
            "PSUBSB",
            "PMINUB",
            "PMINSW",
            "PMAXUB",
            "PMAXSW",
            "PADDB",
            "PADDW",
            "PADDD",
            "PADDQ",
            "PSUBB",
            "PSUBW",
            "PSUBD",
            "PSUBQ",
            "PSLLW",
            "PSLLD",
            "PSLLQ",
            "PSRAW",
            "PSRLW",
            "PSRLD",
            "PSRLQ",
            "PSRAD",
            "PHSUBW",
            "PHSUBD",
            "PHSUBSW",
            "PHADDW",
            "PHADDD",
            "PHADDSW",
            "PMULHRSW",
            "PSIGNB",
            "PSIGNW",
            "PSIGND",
            "PABSB",
            "PABSW",
            "PABSD",
            "DPPD",
            "PHMINPOSUW",
            "MPSADBW",
            "PMAXSB",
            "PMAXSD",
            "PMAXUD",
            "PMINSB",
            "PMINSD",
            "PMINUD",
            "PMAXUW",
            "PMINUW",
            "PMOVSXxx",
            "PMOVZXxx",
            "PMULDQ",
            "PMULLD",
            "ROUNDSD",
            "ROUNDSS",
            "POPCNT",
            "PCMPGTQ",
            "CRC32",
            "PCMPESTRI",
            "PCMPESTRM",
            "PCMPISTRI",
            "PCMPISTRM",
            "PCLMULQDQ"
          ],
          "source_pages": [
            360
          ],
          "children": [],
          "text_preview": "PROGRAMMING WITH INTEL® AVX, FMA, AND INTEL® AVX2\n\n\n          Table 14-5. Promotion of Legacy SIMD ISA to 128-Bit Arithmetic Intel® AVX Instructions (Contd.)\n      VEX.256           VEX.128\n                                                          Instruction                      Reason Not Promoted\n      Encoding          Encoding\n no               yes              PMADDWD, PMADDUBSW                                 VI\n no               yes              PAVGB, PAVGW, PMULUDQ                              VI\n no               yes              PCMPEQB, PCMPEQW, PCMPEQD                          VI\n no               yes              PMULLW, PMULHUW, PMULHW                            VI\n no               yes              PSUBSW, PADDSW, PSADBW                             VI\n no               yes              PADDUSB, PADDUSW, PADDSB                           VI\n no               yes              PSUBUSB, PSUBUSW, PSUBSB                           VI\n no               yes              PMINUB, PMINSW                                     VI\n no               yes              PMAXUB, PMAXSW                                     VI\n no               yes              PADDB, PADDW, PADDD, PADDQ    ",
          "score": 0.5979093313217163
        },
        {
          "id": "parent-1",
          "level": 1,
          "summary": "Pages 360-365 detail the promotion of Legacy SIMD ISA to 128-bit Intel AVX instructions (arithmetic and non-arithmetic), 128-bit non-arithmetic AVX enhancements, and detection processes for AVX, VEX-encoded AES, and VPCLMULQDQ. Table 14-5 covers 128-bit arithmetic promotion: most have VEX.128 (yes) and VEX.256 (no), with reasons like 'VI' (Vector Integer), 'Scalar', or 'Integer'; includes AES instructions (e.g., AESDEC) with 'VI' as 256-bit promotion reason. 128-bit non-arithmetic AVX primitives (Table 14-6) offer same functionality as SIMD prefix-encoded XMM instructions plus enhancements (broadcast, masked move, permute, branch handling like variable blend or packed TEST for floating-point). Table 14-7 details remaining non-arithmetic promotion: instructions (e.g., PBLENDVB, PEXTRW) have VEX.128 (yes), VEX.256 (no), with reasons like 'VI', 'MMX', or 'redundant'. Legacy non-arithmetic ISA promoted to VEX-256 also support VEX-128 (Table 14-3). AVX detection requires CPU support (CPUID.01H:ECX.AVX[28] = 1) and OS support (CPUID.01H:ECX.OSXSAVE[27] = 1, XGETBV verifying XCR0[2:1] = '11b'). VEX-encoded AES and VPCLMULQDQ detection build on AVX detection, requiring their specific CPUID flags (AESNI[25] for AES, PCLMULQDQ[1] for VPCLMULQDQ) plus OS-enabled XMM/YMM state via XGETBV.",
          "key_relationships": {
            "Tables": "Table 14-5 (arithmetic promotion), Table 14-6 (128-bit non-arithmetic enhancements), Table 14-7 (remaining non-arithmetic promotion) are core; Table 14-3 notes VEX-256 promoted non-arithmetic ISA also support VEX-128.",
            "Promotion Reasons": "'VI' (Vector Integer) is a common reason for 256-bit non-promotion across arithmetic (Table 14-5) and non-arithmetic (Table 14-7) instructions.",
            "AVX Detection": "Requires both CPU support (CPUID.01H:ECX.AVX[28]) and OS support (OSXSAVE flag + XGETBV XCR0[2:1] = '11b') to avoid #UD.",
            "AES/VPCLMULQDQ Detection": "Build on AVX detection, adding their specific CPUID flags (AESNI[25] for AES, PCLMULQDQ[1] for VPCLMULQDQ) while retaining OS support checks via XGETBV."
          },
          "source_pages": [
            360,
            361,
            362,
            363,
            364,
            365
          ],
          "children": [
            "leaf-360",
            "leaf-361",
            "leaf-362",
            "leaf-363",
            "leaf-364",
            "leaf-365"
          ],
          "score": 0.5854339599609375
        },
        {
          "id": "leaf-365",
          "level": 0,
          "summary": "This section covers detection sequences for VEX-encoded AES instructions (e.g., VAESDEC, VAESDECLAST, VAESENC, VAESENCLAST, VAESIMC, VAESKEYGENASSIST) and VPCLMULQDQ instructions. Detection of VEX-encoded AES instructions requires checking CPUID.01H:ECX.AES[25] = 1 and application support for Intel AVX, as demonstrated in Example 14-2, which includes CPUID checks for OSXSAVE, AVX, and AESNI feature flags, and using XGETBV to verify OS-enabled XMM and YMM state support. Similarly, detection of VEX-encoded VPCLMULQDQ requires checking CPUID.01H:ECX.PCLMULQDQ[1] = 1 and AVX support, shown in Example 14-3 with CPUID checks for OSXSAVE, AVX, and PCLMULQDQ feature flags, and XGETBV to confirm OS-enabled XMM and YMM state support.",
          "key_terms": [
            "VEX-encoded AES",
            "VPCLMULQDQ",
            "VAESDEC",
            "VAESDECLAST",
            "VAESENC",
            "VAESENCLAST",
            "VAESIMC",
            "VAESKEYGENASSIST",
            "YMM states",
            "CPUID",
            "Intel AVX",
            "XGETBV",
            "XMM states",
            "AESNI feature flag",
            "PCLMULQDQ feature flag",
            "XCR0 register",
            "OSXSAVE"
          ],
          "source_pages": [
            365
          ],
          "children": [],
          "text_preview": "PROGRAMMING WITH INTEL® AVX, FMA, AND INTEL® AVX2\n\n\n\n14.3.1      Detection of VEX-Encoded AES and VPCLMULQDQ\nThe VAESDEC/VAESDECLAST/VAESENC/VAESENCLAST/VAESIMC/VAESKEYGENASSIST instructions operate on\nYMM states. The detection sequence must combine checking for CPUID.01H:ECX.AES[25] = 1 and the sequence\nfor detection application support for Intel AVX.\n\nExample 14-2. Detection of VEX-Encoded Intel® AES-NI Instructions\n\nINT supports_VAESNI()\n{ mov        eax, 1\n   cpuid\n   and       ecx, 01A000000H\n   cmp       ecx, 01A000000H; check OSXSAVE AVX and AESNI feature flags\n    jne      not_supported\n   ; processor supports AVX and VEX-encoded AESNI and XGETBV is enabled by OS\n   mov       ecx, 0; specify 0 for XCR0 register\n   XGETBV              ; result in EDX:EAX\n   and       eax, 06H\n   cmp       eax, 06H; check OS has enabled both XMM and YMM state support\n   jne       not_supported\n   mov       eax, 1\n   jmp       done\nNOT_SUPPORTED:\n   mov       eax, 0\ndone:\n\n\nSimilarly, the detection sequence for VPCLMULQDQ must combine checking for CPUID.01H:ECX.PCLMULQDQ[1] =\n1 and the sequence for detection application support for Intel AVX.\nThis is shown in the pseudocode provided in Example",
          "score": 0.5814453363418579
        }
      ],
      "answer": "CPUID.AVX (CPUID.01H:ECX.AVX[28]) alone is insufficient because it only indicates hardware support for AVX instructions, not operating system support. The operating system must enable XMM and YMM state management; without this, AVX instructions will cause an undefined opcode exception (#UD). Detection requires checking both CPU support (AVX flag) and OS support (CPUID.01H:ECX.OSXSAVE[27] = 1 and XGETBV verifying XCR0[2:1] = '11b' to confirm OS-enabled XMM/YMM state) [363, 364].",
      "query_latency_ms": 11181.72,
      "external_judge": {
        "id": "raptor:relation_cpuid_insufficient",
        "score": 4,
        "correct": true,
        "reason": "The answer correctly explains that CPUID.AVX alone is insufficient because it only indicates hardware support for AVX instructions and does not confirm operating system support for enabling the YMM register state, which is required for AVX instructions to execute without causing an undefined opcode exception (#UD). The answer is consistent with the provided reference."
      }
    },
    {
      "id": "graphrag:relation_cpuid_insufficient",
      "method": "graphrag",
      "query_id": "relation_cpuid_insufficient",
      "category": "relationship-multi-hop",
      "question": "Why is CPUID.AVX alone insufficient proof that AVX instructions can execute?",
      "reference": "The operating system must enable XSAVE/XGETBV and XMM/YMM state management in XCR0; otherwise AVX instructions raise #UD even when CPUID.AVX is set.",
      "gold_pages": [
        323,
        363,
        364
      ],
      "retrieved_pages": [
        360,
        361,
        362,
        363,
        364,
        365
      ],
      "citation_recall": 0.6666666666666666,
      "retrieval_trace": {
        "entities": [
          {
            "id": "128_bit_arithmetic_intel_avx_instructions",
            "name": "128-Bit Arithmetic Intel® AVX Instructions",
            "type": "ISA",
            "descriptions": [
              "Target instructions from Legacy SIMD ISA promotion"
            ],
            "evidence": [],
            "source_pages": [
              360
            ]
          },
          {
            "id": "128_bit_intel_avx_instruction_enhancement",
            "name": "128-bit Intel® AVX Instruction Enhancement",
            "type": "Instruction Set",
            "descriptions": [
              "Enhanced 128-bit AVX instructions including permute and test"
            ],
            "evidence": [],
            "source_pages": [
              362
            ]
          },
          {
            "id": "avx_feature_flag",
            "name": "AVX feature flag",
            "type": "Feature Flag",
            "descriptions": [
              "Indicates hardware support for AVX instructions"
            ],
            "evidence": [],
            "source_pages": [
              364
            ]
          },
          {
            "id": "cpuid_01h_ecx_aes_25_flag",
            "name": "CPUID.01H:ECX.AES[25] flag",
            "type": "CPUID Flag",
            "descriptions": [
              "Prerequisite flag for VEX-encoded AES-NI instruction detection"
            ],
            "evidence": [],
            "source_pages": [
              365
            ]
          },
          {
            "id": "cpuid_01h_ecx_avx",
            "name": "CPUID.01H:ECX.AVX",
            "type": "Feature Flag",
            "descriptions": [
              "CPUID flag indicating AVX instruction support"
            ],
            "evidence": [],
            "source_pages": [
              363
            ]
          },
          {
            "id": "cpuid_01h_ecx_avx_28",
            "name": "CPUID.01H:ECX.AVX[28]",
            "type": "CPUID Feature Flag",
            "descriptions": [
              "Hardware support indicator for Intel AVX"
            ],
            "evidence": [],
            "source_pages": [
              364
            ]
          },
          {
            "id": "intel_avx",
            "name": "Intel AVX",
            "type": "Technology",
            "descriptions": [
              "Provides VEX-encoded data processing instructions for SIMD programming",
              "Instruction set operating on 256-bit YMM register state"
            ],
            "evidence": [],
            "source_pages": [
              361,
              363
            ]
          },
          {
            "id": "legacy_simd_isa",
            "name": "Legacy SIMD ISA",
            "type": "ISA",
            "descriptions": [
              "Source ISA promoted to 128-bit AVX instructions"
            ],
            "evidence": [],
            "source_pages": [
              360
            ]
          },
          {
            "id": "legacy_simd_non_arithmetic_isa",
            "name": "Legacy SIMD non-arithmetic ISA",
            "type": "ISA Component",
            "descriptions": [
              "Legacy SIMD instructions without arithmetic operations"
            ],
            "evidence": [],
            "source_pages": [
              362
            ]
          },
          {
            "id": "osxsave_feature_flag",
            "name": "OSXSAVE feature flag",
            "type": "Feature Flag",
            "descriptions": [
              "Indicates OS support for XSAVE functionality"
            ],
            "evidence": [],
            "source_pages": [
              364
            ]
          },
          {
            "id": "supports_avx",
            "name": "supports_AVX()",
            "type": "Function",
            "descriptions": [
              "Function to detect Intel AVX instruction support"
            ],
            "evidence": [],
            "source_pages": [
              364
            ]
          },
          {
            "id": "vex_encoded_aes_ni_detection_sequence",
            "name": "VEX-encoded AES-NI detection sequence",
            "type": "Detection Sequence",
            "descriptions": [
              "Combines AES flag check and Intel AVX application support check"
            ],
            "evidence": [],
            "source_pages": [
              365
            ]
          },
          {
            "id": "vpermilpd",
            "name": "VPERMILPD",
            "type": "Instruction",
            "descriptions": [
              "Permute double precision floating-point values with controls"
            ],
            "evidence": [],
            "source_pages": [
              362
            ]
          },
          {
            "id": "vpermilps",
            "name": "VPERMILPS",
            "type": "Instruction",
            "descriptions": [
              "Permute single precision floating-point values with controls"
            ],
            "evidence": [],
            "source_pages": [
              362
            ]
          },
          {
            "id": "vtestpd",
            "name": "VTESTPD",
            "type": "Instruction",
            "descriptions": [
              "Set ZF/CF based on packed double precision sign bits"
            ],
            "evidence": [],
            "source_pages": [
              362
            ]
          },
          {
            "id": "vtestps",
            "name": "VTESTPS",
            "type": "Instruction",
            "descriptions": [
              "Set ZF/CF based on packed single precision sign bits"
            ],
            "evidence": [],
            "source_pages": [
              362
            ]
          },
          {
            "id": "xgetbv",
            "name": "XGETBV",
            "type": "Instruction",
            "descriptions": [
              "Instruction to check enabled state in XCR0",
              "Instruction to retrieve XCR0 register value"
            ],
            "evidence": [],
            "source_pages": [
              363,
              364
            ]
          },
          {
            "id": "ymm_state",
            "name": "YMM state",
            "type": "CPU State",
            "descriptions": [
              "SIMD state used by Intel AVX instructions"
            ],
            "evidence": [],
            "source_pages": [
              364
            ]
          }
        ],
        "relationships": [
          {
            "source": "legacy_simd_isa",
            "target": "128_bit_arithmetic_intel_avx_instructions",
            "type": "is promoted to",
            "description": "Legacy SIMD ISA is promoted to 128-bit AVX instructions",
            "evidence_quote": "",
            "source_page": 360
          },
          {
            "source": "128_bit_intel_avx_instruction_enhancement",
            "target": "vpermilpd",
            "type": "Includes",
            "description": "Includes permute double precision floating-point instruction",
            "evidence_quote": "",
            "source_page": 362
          },
          {
            "source": "128_bit_intel_avx_instruction_enhancement",
            "target": "vpermilps",
            "type": "Includes",
            "description": "Includes permute single precision floating-point instruction",
            "evidence_quote": "",
            "source_page": 362
          },
          {
            "source": "128_bit_intel_avx_instruction_enhancement",
            "target": "vtestps",
            "type": "Includes",
            "description": "Includes test for packed single precision sign bits",
            "evidence_quote": "",
            "source_page": 362
          },
          {
            "source": "128_bit_intel_avx_instruction_enhancement",
            "target": "vtestpd",
            "type": "Includes",
            "description": "Includes test for packed double precision sign bits",
            "evidence_quote": "",
            "source_page": 362
          },
          {
            "source": "128_bit_intel_avx_instruction_enhancement",
            "target": "legacy_simd_non_arithmetic_isa",
            "type": "Includes Promoted",
            "description": "Includes promoted legacy SIMD non-arithmetic ISA",
            "evidence_quote": "",
            "source_page": 362
          },
          {
            "source": "cpuid_01h_ecx_avx",
            "target": "intel_avx",
            "type": "Indicates Support",
            "description": "AVX flag indicates support for Intel AVX instructions",
            "evidence_quote": "",
            "source_page": 363
          },
          {
            "source": "supports_avx",
            "target": "osxsave_feature_flag",
            "type": "checks",
            "description": "Checks via CPUID to verify OS support",
            "evidence_quote": "",
            "source_page": 364
          },
          {
            "source": "supports_avx",
            "target": "avx_feature_flag",
            "type": "checks",
            "description": "Checks via CPUID to verify hardware support",
            "evidence_quote": "",
            "source_page": 364
          },
          {
            "source": "supports_avx",
            "target": "xgetbv",
            "type": "uses instruction",
            "description": "Uses to retrieve XCR0 register value",
            "evidence_quote": "",
            "source_page": 364
          },
          {
            "source": "supports_avx",
            "target": "ymm_state",
            "type": "checks support for",
            "description": "Verifies OS enablement of YMM state",
            "evidence_quote": "",
            "source_page": 364
          },
          {
            "source": "cpuid_01h_ecx_avx_28",
            "target": "avx_feature_flag",
            "type": "insufficient indicator for",
            "description": "Hardware flag alone doesn't confirm AVX support",
            "evidence_quote": "",
            "source_page": 364
          },
          {
            "source": "ymm_state",
            "target": "supports_avx",
            "type": "required for",
            "description": "OS-enabled YMM state required for AVX support",
            "evidence_quote": "",
            "source_page": 364
          },
          {
            "source": "vex_encoded_aes_ni_detection_sequence",
            "target": "cpuid_01h_ecx_aes_25_flag",
            "type": "Prerequisite",
            "description": "Detection sequence checks AES[25] flag for support",
            "evidence_quote": "",
            "source_page": 365
          }
        ],
        "communities": [
          {
            "id": "community-4",
            "entity_ids": [
              "128_bit_vector_processing",
              "branch_handling",
              "cpuid_01h_ecx_avx",
              "cpuid_01h_ecx_osxsave",
              "intel_avx",
              "intra_register_manipulation",
              "non_unit_strided_fetching",
              "variable_blend_instructions",
              "vbroadcastss",
              "vex_encoded_instructions",
              "xrstor",
              "xsave"
            ],
            "summary": "This graph community centers on Intel AVX (Advanced Vector Extensions), a technology providing VEX-encoded data processing instructions for SIMD programming, operating on 256-bit YMM registers. It encompasses capabilities like 128-bit vector processing (handling 128-bit SIMD data with VEX-encoded primitives), non-unit-strided fetching (enabling broadcast/masked move), intra-register manipulation (permuting elements), and branch handling (via variable blend instructions with four-operand syntax). VEX-encoded instructions, a core component, enhance flexibility (e.g., for variable blend instructions) and underpin 128-bit processing. Feature flags include CPUID.01H:ECX.AVX (indicating AVX support) and CPUID.01H:ECX.OSXSAVE (a prerequisite for AVX, implying XSAVE/XRSTOR support for extended state management).",
            "key_relationships": [
              {
                "source": "intel_avx",
                "target": "vex_encoded_instructions",
                "type": "includes",
                "description": "employs VEX prefix encoding for data processing"
              },
              {
                "source": "intel_avx",
                "target": "128_bit_vector_processing",
                "type": "supports",
                "description": "via non-arithmetic primitives with VEX.128 encoding"
              },
              {
                "source": "128_bit_vector_processing",
                "target": "non_unit_strided_fetching",
                "type": "enables",
                "description": "via broadcast and masked move SIMD data fetching primitives"
              },
              {
                "source": "128_bit_vector_processing",
                "target": "intra_register_manipulation",
                "type": "enables",
                "description": "via permute primitives for 128-bit SIMD register data"
              },
              {
                "source": "branch_handling",
                "target": "variable_blend_instructions",
                "type": "employs",
                "description": "four-operand syntax for branch conditions"
              },
              {
                "source": "cpuid_01h_ecx_avx",
                "target": "intel_avx",
                "type": "Indicates Support",
                "description": "flag signals AVX instruction support"
              },
              {
                "source": "cpuid_01h_ecx_osxsave",
                "target": "xsave",
                "type": "Implies Support",
                "description": "OSXSAVE=1 implies XSAVE support for extended state saving"
              }
            ],
            "source_pages": [
              361,
              363
            ]
          },
          {
            "id": "community-3",
            "entity_ids": [
              "avx_feature_flag",
              "cpuid_01h_ecx_aes_25_flag",
              "cpuid_01h_ecx_avx_28",
              "cpuid_01h_ecx_xsave_26",
              "intel_avx_application_support",
              "osxsave_feature_flag",
              "supports_avx",
              "vaesdec_instruction",
              "vex_encoded_aes_ni_detection_sequence",
              "xcr0_register",
              "xgetbv",
              "xgetbv_instruction",
              "xmm_ymm_state_support",
              "ymm_state"
            ],
            "summary": "This graph community focuses on detecting hardware and software support for Intel AVX instructions and VEX-encoded AES-NI instructions. Key elements include detection functions (e.g., supports_AVX()), hardware/OS feature flags (e.g., AVX, OSXSAVE), registers (XCR0), instructions (XGETBV), and detection sequences (e.g., VEX-encoded AES-NI detection). It emphasizes checking both hardware capabilities (via CPUID flags) and OS support (via XCR0 register state) to confirm enablement of SIMD states (YMM/XMM) required for these instructions.",
            "key_relationships": [
              {
                "source": "supports_avx",
                "target": [
                  "osxsave_feature_flag",
                  "avx_feature_flag",
                  "xgetbv"
                ],
                "description": "Function checks OS (OSXSAVE) and hardware (AVX) flags, and uses XGETBV to retrieve XCR0 for YMM state verification"
              },
              {
                "source": "vex_encoded_aes_ni_detection_sequence",
                "target": [
                  "cpuid_01h_ecx_aes_25_flag",
                  "intel_avx_application_support",
                  "xgetbv_instruction"
                ],
                "description": "Detection sequence requires AES hardware flag, AVX application support, and uses XGETBV to check XCR0 state"
              },
              {
                "source": "xcr0_register",
                "target": [
                  "xmm_ymm_state_support"
                ],
                "description": "Register stores state enablement status, indicating OS support for XMM/YMM states via XGETBV retrieval"
              },
              {
                "source": "vaesdec_instruction",
                "target": [
                  "vex_encoded_aes_ni_detection_sequence"
                ],
                "description": "VEX-encoded AES-NI instruction requires the detection sequence to verify support"
              },
              {
                "source": [
                  "cpuid_01h_ecx_avx_28",
                  "cpuid_01h_ecx_xsave_26"
                ],
                "target": [
                  "avx_feature_flag",
                  "osxsave_feature_flag"
                ],
                "description": "Hardware CPUID flags alone are insufficient; OS support (via OSXSAVE/XCR0) is required for full AVX/XSAVE enablement"
              }
            ],
            "source_pages": [
              363,
              364,
              365
            ]
          }
        ],
        "explicit_paths": [
          {
            "hints": [
              "CPUID",
              "YMM"
            ],
            "nodes": [
              "CPUID instruction",
              "XSAVE feature set",
              "CR4.OSXSAVE[bit 18]",
              "XCR0",
              "YMM register state"
            ],
            "hops": 4,
            "edges": [
              {
                "source": "cpuid_instruction",
                "target": "xsave_feature_set",
                "type": "Enumerates",
                "description": "Reports support via CPUID.01H:ECX.XSAVE[26] bit",
                "evidence_quote": "",
                "source_page": 323
              },
              {
                "source": "xsave_feature_set",
                "target": "cr4_osxsave_bit_18",
                "type": "Prerequisite",
                "description": "Enabled only if CR4.OSXSAVE[bit 18] is set to 1",
                "evidence_quote": "",
                "source_page": 323
              },
              {
                "source": "cr4_osxsave_bit_18",
                "target": "xcr0",
                "type": "Affects",
                "description": "If 0, treats all XCR0 bits as clear for state management",
                "evidence_quote": "",
                "source_page": 323
              },
              {
                "source": "xcr0",
                "target": "ymm_register_state",
                "type": "Enables",
                "description": "XCR0[2:1] = '11b' enables YMM register state",
                "evidence_quote": "",
                "source_page": 363
              }
            ]
          }
        ]
      },
      "answer": "CPUID.AVX alone is insufficient because hardware support (indicated by the AVX feature flag) does not confirm OS support for enabling the YMM register state required by AVX instructions. The `supports_AVX()` function checks both the AVX feature flag (hardware support) and the OSXSAVE feature flag (OS support for XSAVE functionality), and uses the XGETBV instruction to verify OS enablement of the YMM state via XCR0. Hardware flags alone are insufficient; OS support for YMM state is required [364, 365].",
      "query_latency_ms": 13188.81,
      "external_judge": {
        "id": "graphrag:relation_cpuid_insufficient",
        "score": 4,
        "correct": true,
        "reason": "The answer correctly states that CPUID.AVX alone is insufficient because it only indicates hardware support and does not confirm OS support for enabling the YMM register state required by AVX instructions. The answer is consistent with the information provided in the reference."
      }
    },
    {
      "id": "raptor:relation_cr4_xcr0",
      "method": "raptor",
      "query_id": "relation_cr4_xcr0",
      "category": "relationship-multi-hop",
      "question": "How do CR4.OSXSAVE, XGETBV, XCR0, and AVX state availability depend on one another?",
      "reference": "CR4.OSXSAVE enables the XSAVE feature set and application use of XGETBV; XGETBV reads XCR0, whose XMM/YMM bits must be enabled for AVX state and instructions to be available.",
      "gold_pages": [
        323,
        363,
        364
      ],
      "retrieved_pages": [
        323,
        363,
        364,
        365
      ],
      "citation_recall": 1.0,
      "retrieval_trace": [
        {
          "id": "parent-2",
          "level": 1,
          "summary": "The XSAVE feature set manages state components, distinguishing between XSAVE-enabled (requiring XCR0 configuration) and XSAVE-managed (non-XSAVE-enabled) components. XSAVE-enabled features have user state components; their registers remain unmodified and instructions cause invalid-opcode exceptions (#UD) if XCR0 bits are clear. XSAVE is enabled only when CR4.OSXSAVE=1; if CR4.OSXSAVE=0, XCR0 bits are treated as clear, blocking XSAVE-enabled feature instructions. XSAVE-managed but non-XSAVE-enabled components (x87, SSE, PT, PKRU, PASID, CET, HDC, UINTR, LBR, HWP) allow modification/execution regardless of CR4.OSXSAVE/XCR0. Enumeration uses CPUID: CPUID.01H:ECX.XSAVE[26] indicates general XSAVE support (1=supports XGETBV/XRSTOR/XSAVE/XSETBV and CPUID.0DH; 0=does not). CPUID.0DH sub-leaves: 00H provides user state component bitmap (EDX:EAX), XSAVE area size for all components (ECX), and current XCR0 bits size (EBX); 01H: EAX[0] for XSAVEOPT support, EAX[1] for compaction extensions.",
          "key_relationships": [
            "XSAVE-enabled features require XCR0 configuration; XCR0 bits clear → registers unmodified/instructions cause #UD",
            "XSAVE enabled only if CR4.OSXSAVE=1; CR4.OSXSAVE=0 → XCR0 bits treated as clear, blocking XSAVE-enabled instructions",
            "XSAVE-managed non-enabled components (x87, SSE, etc.) modified/executed regardless of CR4.OSXSAVE/XCR0",
            "CPUID.01H:ECX.XSAVE[26] = 1 → supports XGETBV/XRSTOR/XSAVE/XSETBV and CPUID.0DH",
            "CPUID.0DH sub-leaf 00H → user state bitmap (EDX:EAX), XSAVE area size (all components: ECX; current XCR0 bits: EBX)",
            "CPUID.0DH sub-leaf 01H: EAX[0] = XSAVEOPT support; EAX[1] = compaction extensions"
          ],
          "source_pages": [
            323
          ],
          "children": [
            "leaf-323"
          ],
          "score": 0.6595778465270996
        },
        {
          "id": "leaf-323",
          "level": 0,
          "summary": "The XSAVE feature set manages state components, with XSAVE-enabled features (those with user state components) requiring XCR0 configuration; their registers are unmodified/instructions cause invalid-opcode exceptions (#UD) if XCR0 bits are clear. XSAVE is enabled only if CR4.OSXSAVE=1; if 0, XCR0 bits are treated as clear, blocking feature instructions. Some state components (x87, SSE, PT, PKRU, PASID, CET, HDC, UINTR, LBR, HWP) are XSAVE-managed but not XSAVE-enabled, allowing modification/execution regardless of CR4.OSXSAVE/XCR0. Enumeration of XSAVE support uses CPUID: CPUID.01H:ECX.XSAVE[26] indicates general XSAVE support (0: no XGETBV/XRSTOR/XSAVE/XSETBV or CPUID.0DH; 1: supports these instructions and CPUID.0DH). CPUID.0DH sub-leaves: 00H provides user state component bitmap (EDX:EAX), XSAVE area size for all components (ECX), and for current XCR0 bits (EBX); 01H: EAX[0] for XSAVEOPT support, EAX[1] for compaction extensions.",
          "key_terms": [
            "XSAVE feature set",
            "XCR0",
            "XSAVE-enabled",
            "CR4.OSXSAVE",
            "invalid-opcode exception (#UD)",
            "x87 state",
            "SSE state",
            "PT state",
            "PKRU state",
            "PASID state",
            "CET state",
            "HDC state",
            "UINTR state",
            "LBR state",
            "HWP state",
            "XSAVE-managed",
            "CPUID instruction",
            "CPUID.01H:ECX.XSAVE[26]",
            "XGETBV",
            "XRSTOR",
            "XRSTORS",
            "XSAVE",
            "XSAVEC",
            "XSAVEOPT",
            "XSAVES",
            "XSETBV",
            "CPUID.0DH",
            "sub-leaves",
            "user state components",
            "XSAVE area",
            "bitmap",
            "compaction extensions"
          ],
          "source_pages": [
            323
          ],
          "children": [],
          "text_preview": "MANAGING STATE USING THE XSAVE FEATURE SET\n\n\nSome XSAVE-supported features can be used only if XCR0 has been configured so that the features’ state compo-\nnents can be managed by the XSAVE feature set. (This applies only to features with user state components.) Such\nstate components and features are XSAVE-enabled. In general, the processor will not modify (or allow modifica-\ntion of) the registers of a state component of an XSAVE-enabled feature if the bit corresponding to that state\ncomponent is clear in XCR0. (If software clears such a bit in XCR0, the processor preserves the corresponding state\ncomponent.) If an XSAVE-enabled feature has not been fully enabled in XCR0, execution of any instruction defined\nfor that feature causes an invalid-opcode exception (#UD).\nAs will be explained in Section 13.3, the XSAVE feature set is enabled only if CR4.OSXSAVE[bit 18] = 1. If\nCR4.OSXSAVE = 0, the processor treats XSAVE-enabled state features and their state components as if all bits in\nXCR0 were clear; the state components cannot be modified and the features’ instructions cannot be executed.\nThe state components for x87 state, for SSE state, for PT state, for PKRU state, for PASID state",
          "score": 0.6567427515983582
        },
        {
          "id": "leaf-364",
          "level": 0,
          "summary": "Describes the recommended process for detecting Intel® AVX instructions, including pseudocode for a supports_AVX() function. The process involves using CPUID to check OSXSAVE and AVX feature flags in ECX; if set, XGETBV (with ECX=0) is used to verify the operating system has enabled XMM and YMM state support by checking EAX after AND with 06H. A note warns against relying exclusively on CPUID.01H:ECX.AVX[28] or XSAVE[26], as these indicate hardware support only, not operating system support; without OS-enabled YMM state management, Intel AVX instructions will cause #UD. These steps also apply to enhanced 128-bit SIMD floating-point instructions in Intel AVX (using VEX prefix-encoding) operating on YMM states.",
          "key_terms": [
            "Intel® AVX",
            "detection process",
            "pseudocode",
            "supports_AVX()",
            "CPUID",
            "OSXSAVE",
            "AVX feature flags",
            "ECX",
            "XGETBV",
            "XMM state",
            "YMM state",
            "OS support",
            "hardware support",
            "#UD",
            "enhanced 128-bit SIMD floating-point instructions",
            "VEX prefix-encoding"
          ],
          "source_pages": [
            364
          ],
          "children": [],
          "text_preview": "PROGRAMMING WITH INTEL® AVX, FMA, AND INTEL® AVX2\n\n\nThe following pseudocode illustrates this recommended application Intel AVX detection process:\n\nExample 14-1. Detection of Intel® AVX Instruction\n\nINT supports_AVX()\n{ mov        eax, 1\n   cpuid\n   and       ecx, 018000000H\n   cmp       ecx, 018000000H; check both OSXSAVE and AVX feature flags\n    jne      not_supported\n   ; processor supports AVX instructions and XGETBV is enabled by OS\n   mov       ecx, 0; specify 0 for XCR0 register\n   XGETBV              ; result in EDX:EAX\n   and       eax, 06H\n   cmp       eax, 06H; check OS has enabled both XMM and YMM state support\n   jne       not_supported\n   mov       eax, 1\n   jmp       done\nNOT_SUPPORTED:\n   mov       eax, 0\n   done:\n}\n\n\n                                                          NOTE\n         It is unwise for an application to rely exclusively on CPUID.01H:ECX.AVX[28] or at all on\n         CPUID.01H:ECX.XSAVE[26]: These indicate hardware support but not operating system support. If\n         YMM state management is not enabled by an operating systems, Intel AVX instructions will #UD\n         regardless of CPUID.01H:ECX.AVX[28]. “CPUID.01H:ECX.XSAVE[26] = 1” does not gua",
          "score": 0.47843387722969055
        },
        {
          "id": "leaf-365",
          "level": 0,
          "summary": "This section covers detection sequences for VEX-encoded AES instructions (e.g., VAESDEC, VAESDECLAST, VAESENC, VAESENCLAST, VAESIMC, VAESKEYGENASSIST) and VPCLMULQDQ instructions. Detection of VEX-encoded AES instructions requires checking CPUID.01H:ECX.AES[25] = 1 and application support for Intel AVX, as demonstrated in Example 14-2, which includes CPUID checks for OSXSAVE, AVX, and AESNI feature flags, and using XGETBV to verify OS-enabled XMM and YMM state support. Similarly, detection of VEX-encoded VPCLMULQDQ requires checking CPUID.01H:ECX.PCLMULQDQ[1] = 1 and AVX support, shown in Example 14-3 with CPUID checks for OSXSAVE, AVX, and PCLMULQDQ feature flags, and XGETBV to confirm OS-enabled XMM and YMM state support.",
          "key_terms": [
            "VEX-encoded AES",
            "VPCLMULQDQ",
            "VAESDEC",
            "VAESDECLAST",
            "VAESENC",
            "VAESENCLAST",
            "VAESIMC",
            "VAESKEYGENASSIST",
            "YMM states",
            "CPUID",
            "Intel AVX",
            "XGETBV",
            "XMM states",
            "AESNI feature flag",
            "PCLMULQDQ feature flag",
            "XCR0 register",
            "OSXSAVE"
          ],
          "source_pages": [
            365
          ],
          "children": [],
          "text_preview": "PROGRAMMING WITH INTEL® AVX, FMA, AND INTEL® AVX2\n\n\n\n14.3.1      Detection of VEX-Encoded AES and VPCLMULQDQ\nThe VAESDEC/VAESDECLAST/VAESENC/VAESENCLAST/VAESIMC/VAESKEYGENASSIST instructions operate on\nYMM states. The detection sequence must combine checking for CPUID.01H:ECX.AES[25] = 1 and the sequence\nfor detection application support for Intel AVX.\n\nExample 14-2. Detection of VEX-Encoded Intel® AES-NI Instructions\n\nINT supports_VAESNI()\n{ mov        eax, 1\n   cpuid\n   and       ecx, 01A000000H\n   cmp       ecx, 01A000000H; check OSXSAVE AVX and AESNI feature flags\n    jne      not_supported\n   ; processor supports AVX and VEX-encoded AESNI and XGETBV is enabled by OS\n   mov       ecx, 0; specify 0 for XCR0 register\n   XGETBV              ; result in EDX:EAX\n   and       eax, 06H\n   cmp       eax, 06H; check OS has enabled both XMM and YMM state support\n   jne       not_supported\n   mov       eax, 1\n   jmp       done\nNOT_SUPPORTED:\n   mov       eax, 0\ndone:\n\n\nSimilarly, the detection sequence for VPCLMULQDQ must combine checking for CPUID.01H:ECX.PCLMULQDQ[1] =\n1 and the sequence for detection application support for Intel AVX.\nThis is shown in the pseudocode provided in Example",
          "score": 0.47292983531951904
        },
        {
          "id": "leaf-363",
          "level": 0,
          "summary": "The content includes a continuation of Table 14-7, which lists Legacy SIMD ISA instructions (e.g., PBLENDVB, PBLENDW, PEXTRW/B/D/Q, PINSRB/D/Q) promoted to 128-bit non-arithmetic Intel AVX instructions (VEX.256 encoding: no, VEX.128 encoding: yes) with 'VI' (Vector Integer) as the reason for not being promoted to 256-bit. Section 14.3 covers detection of Intel AVX instructions, requiring checks for OS support (CPUID.01H:ECX.OSXSAVE[27] = 1, XGETBV verifying XCR0[2:1] = '11b' for XMM/YMM state enable) and processor support (CPUID.01H:ECX.AVX[28] = 1), with a recommended sequence involving these steps.",
          "key_terms": [
            "Legacy SIMD ISA",
            "Intel AVX",
            "VEX.256 Encoding",
            "VEX.128 Encoding",
            "PBLENDVB",
            "PBLENDW",
            "PEXTRW",
            "PEXTRB",
            "PEXTRD",
            "PEXTRQ",
            "PINSRB",
            "PINSRD",
            "PINSRQ",
            "VI (Vector Integer)",
            "YMM register state",
            "XGETBV instruction",
            "XSAVE/XRSTOR",
            "CPUID.01H:ECX.OSXSAVE[27]",
            "XCR0[2:1] = '11b'",
            "CPUID.01H:ECX.AVX[28]"
          ],
          "source_pages": [
            363
          ],
          "children": [],
          "text_preview": "PROGRAMMING WITH INTEL® AVX, FMA, AND INTEL® AVX2\n\n\n       Table 14-7. Promotion of Legacy SIMD ISA to 128-Bit Non-Arithmetic Intel® AVX instruction (Contd.)\n     VEX.256            VEX.128\n                                                                Instruction                              Reason Not Promoted\n     Encoding           Encoding\n\nno                yes                  PBLENDVB, PBLENDW                                            VI\nno                yes                  PEXTRW, PEXTRB, PEXTRD, PEXTRQ                               VI\nno                yes                  PINSRB, PINSRD, PINSRQ                                       VI\n\nDescription of column “Reason not promoted”:\n•    MMX: Instructions referencing MMX registers do not support VEX.\n•    Scalar: Scalar instructions are not promoted to 256-bit.\n•    VI: “Vector Integer” instructions are not promoted to 256-bit.\n•    Note 1: MOVLPD/PS and MOVHPD/PS are not promoted to 256-bit. The equivalent functionality are provided\n     by VINSERTF128 and VEXTRACTF128 instructions as the existing instructions have no natural 256b extension\n•    Note 3: It is expected that using 128-bit INSERTPS followed by a VINSERTF1",
          "score": 0.4215521216392517
        }
      ],
      "answer": "CR4.OSXSAVE, XGETBV, XCR0, and AVX state availability are interdependent as follows:  \n\n- **CR4.OSXSAVE enables XSAVE functionality**: XSAVE (and thus XCR0 configuration) is only enabled when CR4.OSXSAVE=1. If CR4.OSXSAVE=0, XCR0 bits are treated as clear, blocking XSAVE-enabled feature instructions (including AVX) [323].  \n\n- **XCR0 controls AVX state availability**: AVX is an XSAVE-enabled feature, requiring XCR0 configuration. Its instructions cause invalid-opcode exceptions (#UD) if XCR0 bits for XMM/YMM state are clear. For AVX, XCR0[2:1] must be '11b' to enable XMM and YMM state support [363, 364].  \n\n- **XGETBV reads XCR0 to verify OS support**: To confirm AVX state availability, XGETBV (with ECX=0) is used to read XCR0. Checking EAX after XGETBV (AND with 06H) verifies if the OS has enabled XMM/YMM state via XCR0[2:1] [364].  \n\n- **AVX requires all three**: AVX instructions are only available if CR4.OSXSAVE=1 (enabling XSAVE), XCR0[2:1]='11b' (enabling AVX state, checked via XGETBV), and CPUID indicates AVX hardware support (CPUID.01H:ECX.AVX[28]=1) [363, 364].  \n\n[323, 363, 364]",
      "query_latency_ms": 22867.209,
      "external_judge": {
        "id": "raptor:relation_cr4_xcr0",
        "score": 4,
        "correct": true,
        "reason": "The answer accurately describes the interdependence between CR4.OSXSAVE, XGETBV, XCR0, and AVX state availability, including the role of CR4.OSXSAVE in enabling XSAVE functionality, XCR0 in controlling AVX state availability, XGETBV in reading XCR0, and the requirement for AVX instructions to have both CR4.OSXSAVE and XCR0 configured correctly. The answer is detailed and aligns with the provided reference."
      }
    },
    {
      "id": "graphrag:relation_cr4_xcr0",
      "method": "graphrag",
      "query_id": "relation_cr4_xcr0",
      "category": "relationship-multi-hop",
      "question": "How do CR4.OSXSAVE, XGETBV, XCR0, and AVX state availability depend on one another?",
      "reference": "CR4.OSXSAVE enables the XSAVE feature set and application use of XGETBV; XGETBV reads XCR0, whose XMM/YMM bits must be enabled for AVX state and instructions to be available.",
      "gold_pages": [
        323,
        363,
        364
      ],
      "retrieved_pages": [
        323,
        363,
        364,
        365
      ],
      "citation_recall": 1.0,
      "retrieval_trace": {
        "entities": [
          {
            "id": "cpuid_instruction",
            "name": "CPUID instruction",
            "type": "Instruction",
            "descriptions": [
              "Enumerates XSAVE support via sub-leaves (e.g., 01H, 0DH)"
            ],
            "evidence": [],
            "source_pages": [
              323
            ]
          },
          {
            "id": "cr4_osxsave_bit_18",
            "name": "CR4.OSXSAVE[bit 18]",
            "type": "Register Bit",
            "descriptions": [
              "Enables XSAVE feature set when set to 1; disables if 0"
            ],
            "evidence": [],
            "source_pages": [
              323
            ]
          },
          {
            "id": "invalid_opcode_exception_#ud",
            "name": "invalid-opcode exception (#UD)",
            "type": "Exception",
            "descriptions": [
              "Triggered by executing unenabled XSAVE feature instructions"
            ],
            "evidence": [],
            "source_pages": [
              323
            ]
          },
          {
            "id": "user_state_components",
            "name": "User state components",
            "type": "State Component",
            "descriptions": [
              "State elements (e.g., x87, SSE) managed or not by XSAVE"
            ],
            "evidence": [],
            "source_pages": [
              323
            ]
          },
          {
            "id": "vex_encoded_aes_ni_detection_sequence",
            "name": "VEX-encoded AES-NI detection sequence",
            "type": "Detection Sequence",
            "descriptions": [
              "Combines AES flag check and Intel AVX application support check"
            ],
            "evidence": [],
            "source_pages": [
              365
            ]
          },
          {
            "id": "xcr0",
            "name": "XCR0",
            "type": "Register",
            "descriptions": [
              "Controls management of XSAVE-enabled state components via bit settings",
              "Extended control register holding state enable bits"
            ],
            "evidence": [],
            "source_pages": [
              323,
              363
            ]
          },
          {
            "id": "xcr0_register",
            "name": "XCR0 register",
            "type": "Register",
            "descriptions": [
              "Stores state management enablement status",
              "Queried via XGETBV to check XMM/YMM state support"
            ],
            "evidence": [],
            "source_pages": [
              364,
              365
            ]
          },
          {
            "id": "xgetbv",
            "name": "XGETBV",
            "type": "Instruction",
            "descriptions": [
              "Instruction to check enabled state in XCR0",
              "Instruction to retrieve XCR0 register value"
            ],
            "evidence": [],
            "source_pages": [
              363,
              364
            ]
          },
          {
            "id": "xgetbv_instruction",
            "name": "XGETBV instruction",
            "type": "Instruction",
            "descriptions": [
              "Retrieves XCR0 value to check OS-enabled XMM/YMM support"
            ],
            "evidence": [],
            "source_pages": [
              365
            ]
          },
          {
            "id": "xmm_ymm_state_support",
            "name": "XMM/YMM state support",
            "type": "concept",
            "descriptions": [],
            "evidence": [],
            "source_pages": [
              365
            ]
          },
          {
            "id": "xsave_enabled_features",
            "name": "XSAVE-enabled features",
            "type": "Feature",
            "descriptions": [
              "Features with user state components managed by XSAVE via XCR0"
            ],
            "evidence": [],
            "source_pages": [
              323
            ]
          },
          {
            "id": "xsave_feature_set",
            "name": "XSAVE feature set",
            "type": "Feature Set",
            "descriptions": [
              "Manages state components via XCR0 and CR4.OSXSAVE configuration"
            ],
            "evidence": [],
            "source_pages": [
              323
            ]
          },
          {
            "id": "ymm_register_state",
            "name": "YMM register state",
            "type": "Register State",
            "descriptions": [
              "256-bit register state used by Intel AVX instructions"
            ],
            "evidence": [],
            "source_pages": [
              363
            ]
          }
        ],
        "relationships": [
          {
            "source": "xsave_feature_set",
            "target": "cr4_osxsave_bit_18",
            "type": "Prerequisite",
            "description": "Enabled only if CR4.OSXSAVE[bit 18] is set to 1",
            "evidence_quote": "",
            "source_page": 323
          },
          {
            "source": "xcr0",
            "target": "xsave_enabled_features",
            "type": "Controls",
            "description": "Bit settings determine management of their state components",
            "evidence_quote": "",
            "source_page": 323
          },
          {
            "source": "xsave_enabled_features",
            "target": "invalid_opcode_exception_#ud",
            "type": "Causes",
            "description": "Executing unenabled instructions triggers #UD",
            "evidence_quote": "",
            "source_page": 323
          },
          {
            "source": "cpuid_instruction",
            "target": "xsave_feature_set",
            "type": "Enumerates",
            "description": "Reports support via CPUID.01H:ECX.XSAVE[26] bit",
            "evidence_quote": "",
            "source_page": 323
          },
          {
            "source": "cr4_osxsave_bit_18",
            "target": "xcr0",
            "type": "Affects",
            "description": "If 0, treats all XCR0 bits as clear for state management",
            "evidence_quote": "",
            "source_page": 323
          },
          {
            "source": "xsave_feature_set",
            "target": "user_state_components",
            "type": "Manages",
            "description": "Controls modification based on XCR0 and CR4.OSXSAVE settings",
            "evidence_quote": "",
            "source_page": 323
          },
          {
            "source": "xsave_enabled_features",
            "target": "xcr0",
            "type": "Requires",
            "description": "Need XCR0 configuration to manage their state components",
            "evidence_quote": "",
            "source_page": 323
          },
          {
            "source": "xgetbv",
            "target": "xcr0",
            "type": "Checks",
            "description": "XGETBV verifies XCR0[2:1] = '11b' for state enable",
            "evidence_quote": "",
            "source_page": 363
          },
          {
            "source": "xcr0",
            "target": "ymm_register_state",
            "type": "Enables",
            "description": "XCR0[2:1] = '11b' enables YMM register state",
            "evidence_quote": "",
            "source_page": 363
          },
          {
            "source": "xgetbv",
            "target": "xcr0_register",
            "type": "retrieves",
            "description": "Instruction retrieves value of XCR0 register",
            "evidence_quote": "",
            "source_page": 364
          },
          {
            "source": "xgetbv_instruction",
            "target": "xcr0_register",
            "type": "Accesses",
            "description": "XGETBV retrieves XCR0 register value",
            "evidence_quote": "",
            "source_page": 365
          },
          {
            "source": "xcr0_register",
            "target": "xmm_ymm_state_support",
            "type": "Indicates",
            "description": "XCR0 state indicates XMM/YMM enablement by OS",
            "evidence_quote": "",
            "source_page": 365
          },
          {
            "source": "vex_encoded_aes_ni_detection_sequence",
            "target": "xgetbv_instruction",
            "type": "Uses",
            "description": "Detection uses XGETBV to check XCR0 state",
            "evidence_quote": "",
            "source_page": 365
          }
        ],
        "communities": [
          {
            "id": "community-5",
            "entity_ids": [
              "cpuid_instruction",
              "cr4_osxsave_bit_18",
              "invalid_opcode_exception_#ud",
              "user_state_components",
              "xcr0",
              "xsave_enabled_features",
              "xsave_feature_set",
              "xsaveopt_instruction",
              "ymm_register_state"
            ],
            "summary": "This graph community focuses on the XSAVE feature set, which manages user state components (e.g., YMM register state) through configuration of CR4.OSXSAVE[bit 18] and XCR0. The CPUID instruction enumerates support for the XSAVE feature set and specific instructions like XSAVEOPT. The XSAVE feature set is enabled only if CR4.OSXSAVE[bit 18] is set, which affects XCR0's state management. XCR0 controls XSAVE-enabled features via bit settings, determining which state components are managed; unenabled features trigger invalid-opcode exceptions (#UD). Additionally, XCR0 enables specific states such as YMM register state when configured appropriately.",
            "key_relationships": [
              {
                "source": "xsave_feature_set",
                "target": "cr4_osxsave_bit_18",
                "type": "Prerequisite",
                "description": "Enabled only if CR4.OSXSAVE[bit 18] is set to 1"
              },
              {
                "source": "cpuid_instruction",
                "target": "xsave_feature_set",
                "type": "Enumerates",
                "description": "Reports support via CPUID.01H:ECX.XSAVE[26] bit"
              },
              {
                "source": "cpuid_instruction",
                "target": "xsaveopt_instruction",
                "type": "Enumerates",
                "description": "Support indicated by CPUID.0DH.01H.EAX[0] bit"
              },
              {
                "source": "xcr0",
                "target": "xsave_enabled_features",
                "type": "Controls",
                "description": "Bit settings determine management of their state components"
              },
              {
                "source": "cr4_osxsave_bit_18",
                "target": "xcr0",
                "type": "Affects",
                "description": "If 0, treats all XCR0 bits as clear for state management"
              },
              {
                "source": "xsave_enabled_features",
                "target": "invalid_opcode_exception_#ud",
                "type": "Causes",
                "description": "Executing unenabled instructions triggers #UD"
              },
              {
                "source": "xcr0",
                "target": "ymm_register_state",
                "type": "Enables",
                "description": "XCR0[2:1] = '11b' enables YMM register state"
              }
            ],
            "source_pages": [
              323,
              363
            ]
          },
          {
            "id": "community-3",
            "entity_ids": [
              "avx_feature_flag",
              "cpuid_01h_ecx_aes_25_flag",
              "cpuid_01h_ecx_avx_28",
              "cpuid_01h_ecx_xsave_26",
              "intel_avx_application_support",
              "osxsave_feature_flag",
              "supports_avx",
              "vaesdec_instruction",
              "vex_encoded_aes_ni_detection_sequence",
              "xcr0_register",
              "xgetbv",
              "xgetbv_instruction",
              "xmm_ymm_state_support",
              "ymm_state"
            ],
            "summary": "This graph community focuses on detecting hardware and software support for Intel AVX instructions and VEX-encoded AES-NI instructions. Key elements include detection functions (e.g., supports_AVX()), hardware/OS feature flags (e.g., AVX, OSXSAVE), registers (XCR0), instructions (XGETBV), and detection sequences (e.g., VEX-encoded AES-NI detection). It emphasizes checking both hardware capabilities (via CPUID flags) and OS support (via XCR0 register state) to confirm enablement of SIMD states (YMM/XMM) required for these instructions.",
            "key_relationships": [
              {
                "source": "supports_avx",
                "target": [
                  "osxsave_feature_flag",
                  "avx_feature_flag",
                  "xgetbv"
                ],
                "description": "Function checks OS (OSXSAVE) and hardware (AVX) flags, and uses XGETBV to retrieve XCR0 for YMM state verification"
              },
              {
                "source": "vex_encoded_aes_ni_detection_sequence",
                "target": [
                  "cpuid_01h_ecx_aes_25_flag",
                  "intel_avx_application_support",
                  "xgetbv_instruction"
                ],
                "description": "Detection sequence requires AES hardware flag, AVX application support, and uses XGETBV to check XCR0 state"
              },
              {
                "source": "xcr0_register",
                "target": [
                  "xmm_ymm_state_support"
                ],
                "description": "Register stores state enablement status, indicating OS support for XMM/YMM states via XGETBV retrieval"
              },
              {
                "source": "vaesdec_instruction",
                "target": [
                  "vex_encoded_aes_ni_detection_sequence"
                ],
                "description": "VEX-encoded AES-NI instruction requires the detection sequence to verify support"
              },
              {
                "source": [
                  "cpuid_01h_ecx_avx_28",
                  "cpuid_01h_ecx_xsave_26"
                ],
                "target": [
                  "avx_feature_flag",
                  "osxsave_feature_flag"
                ],
                "description": "Hardware CPUID flags alone are insufficient; OS support (via OSXSAVE/XCR0) is required for full AVX/XSAVE enablement"
              }
            ],
            "source_pages": [
              363,
              364,
              365
            ]
          }
        ],
        "explicit_paths": []
      },
      "answer": "CR4.OSXSAVE, XGETBV, XCR0, and AVX state availability are interdependent as follows:  \n\n- **CR4.OSXSAVE (bit 18)** enables the XSAVE feature set when set to 1; if 0, all XCR0 bits are treated as clear for state management [323]. It is a prerequisite for XSAVE feature set functionality, including AVX state management.  \n\n- **XCR0** controls management of XSAVE-enabled state components via bit settings. For AVX, XCR0[2:1] = '11b' specifically enables YMM register state (256-bit state used by AVX instructions) [363].  \n\n- **XGETBV** is an instruction that retrieves the XCR0 register value [363, 364, 365]. It is used to check XCR0[2:1] = '11b' to verify OS-enabled XMM/YMM state support, which is required for AVX availability [363, 365].  \n\n- **AVX state availability** depends on both CR4.OSXSAVE being set (to enable XSAVE) and XCR0[2:1] = '11b' (to enable YMM state). Without CR4.OSXSAVE enabled, XCR0 bits are ignored, and unenabled XSAVE features (including AVX) trigger invalid-opcode exceptions (#UD) [323].  \n\nThus, CR4.OSXSAVE enables XSAVE, XCR0 configures AVX state via specific bits, XGETBV checks XCR0 to confirm AVX state enablement, and all are required for AVX state availability.",
      "query_latency_ms": 18454.377,
      "external_judge": {
        "id": "graphrag:relation_cr4_xcr0",
        "score": 4,
        "correct": true,
        "reason": "The answer correctly explains the interdependence between CR4.OSXSAVE, XGETBV, XCR0, and AVX state availability, including the role of CR4.OSXSAVE in enabling XSAVE, XCR0 in configuring AVX state, and XGETBV in verifying XCR0 configuration. The answer is consistent with the information provided in the reference."
      }
    },
    {
      "id": "raptor:relation_xcr0_ud",
      "method": "raptor",
      "query_id": "relation_xcr0_ud",
      "category": "relationship-multi-hop",
      "question": "What happens when an XSAVE-enabled feature is not fully enabled in XCR0, and how does that explain AVX #UD behavior?",
      "reference": "Instructions for a feature not fully enabled in XCR0 raise invalid-opcode #UD; AVX likewise #UDs when the OS has not enabled both XMM and YMM state even if the processor advertises AVX.",
      "gold_pages": [
        323,
        364
      ],
      "retrieved_pages": [
        323,
        363,
        364,
        365
      ],
      "citation_recall": 1.0,
      "retrieval_trace": [
        {
          "id": "leaf-323",
          "level": 0,
          "summary": "The XSAVE feature set manages state components, with XSAVE-enabled features (those with user state components) requiring XCR0 configuration; their registers are unmodified/instructions cause invalid-opcode exceptions (#UD) if XCR0 bits are clear. XSAVE is enabled only if CR4.OSXSAVE=1; if 0, XCR0 bits are treated as clear, blocking feature instructions. Some state components (x87, SSE, PT, PKRU, PASID, CET, HDC, UINTR, LBR, HWP) are XSAVE-managed but not XSAVE-enabled, allowing modification/execution regardless of CR4.OSXSAVE/XCR0. Enumeration of XSAVE support uses CPUID: CPUID.01H:ECX.XSAVE[26] indicates general XSAVE support (0: no XGETBV/XRSTOR/XSAVE/XSETBV or CPUID.0DH; 1: supports these instructions and CPUID.0DH). CPUID.0DH sub-leaves: 00H provides user state component bitmap (EDX:EAX), XSAVE area size for all components (ECX), and for current XCR0 bits (EBX); 01H: EAX[0] for XSAVEOPT support, EAX[1] for compaction extensions.",
          "key_terms": [
            "XSAVE feature set",
            "XCR0",
            "XSAVE-enabled",
            "CR4.OSXSAVE",
            "invalid-opcode exception (#UD)",
            "x87 state",
            "SSE state",
            "PT state",
            "PKRU state",
            "PASID state",
            "CET state",
            "HDC state",
            "UINTR state",
            "LBR state",
            "HWP state",
            "XSAVE-managed",
            "CPUID instruction",
            "CPUID.01H:ECX.XSAVE[26]",
            "XGETBV",
            "XRSTOR",
            "XRSTORS",
            "XSAVE",
            "XSAVEC",
            "XSAVEOPT",
            "XSAVES",
            "XSETBV",
            "CPUID.0DH",
            "sub-leaves",
            "user state components",
            "XSAVE area",
            "bitmap",
            "compaction extensions"
          ],
          "source_pages": [
            323
          ],
          "children": [],
          "text_preview": "MANAGING STATE USING THE XSAVE FEATURE SET\n\n\nSome XSAVE-supported features can be used only if XCR0 has been configured so that the features’ state compo-\nnents can be managed by the XSAVE feature set. (This applies only to features with user state components.) Such\nstate components and features are XSAVE-enabled. In general, the processor will not modify (or allow modifica-\ntion of) the registers of a state component of an XSAVE-enabled feature if the bit corresponding to that state\ncomponent is clear in XCR0. (If software clears such a bit in XCR0, the processor preserves the corresponding state\ncomponent.) If an XSAVE-enabled feature has not been fully enabled in XCR0, execution of any instruction defined\nfor that feature causes an invalid-opcode exception (#UD).\nAs will be explained in Section 13.3, the XSAVE feature set is enabled only if CR4.OSXSAVE[bit 18] = 1. If\nCR4.OSXSAVE = 0, the processor treats XSAVE-enabled state features and their state components as if all bits in\nXCR0 were clear; the state components cannot be modified and the features’ instructions cannot be executed.\nThe state components for x87 state, for SSE state, for PT state, for PKRU state, for PASID state",
          "score": 0.6770113110542297
        },
        {
          "id": "parent-2",
          "level": 1,
          "summary": "The XSAVE feature set manages state components, distinguishing between XSAVE-enabled (requiring XCR0 configuration) and XSAVE-managed (non-XSAVE-enabled) components. XSAVE-enabled features have user state components; their registers remain unmodified and instructions cause invalid-opcode exceptions (#UD) if XCR0 bits are clear. XSAVE is enabled only when CR4.OSXSAVE=1; if CR4.OSXSAVE=0, XCR0 bits are treated as clear, blocking XSAVE-enabled feature instructions. XSAVE-managed but non-XSAVE-enabled components (x87, SSE, PT, PKRU, PASID, CET, HDC, UINTR, LBR, HWP) allow modification/execution regardless of CR4.OSXSAVE/XCR0. Enumeration uses CPUID: CPUID.01H:ECX.XSAVE[26] indicates general XSAVE support (1=supports XGETBV/XRSTOR/XSAVE/XSETBV and CPUID.0DH; 0=does not). CPUID.0DH sub-leaves: 00H provides user state component bitmap (EDX:EAX), XSAVE area size for all components (ECX), and current XCR0 bits size (EBX); 01H: EAX[0] for XSAVEOPT support, EAX[1] for compaction extensions.",
          "key_relationships": [
            "XSAVE-enabled features require XCR0 configuration; XCR0 bits clear → registers unmodified/instructions cause #UD",
            "XSAVE enabled only if CR4.OSXSAVE=1; CR4.OSXSAVE=0 → XCR0 bits treated as clear, blocking XSAVE-enabled instructions",
            "XSAVE-managed non-enabled components (x87, SSE, etc.) modified/executed regardless of CR4.OSXSAVE/XCR0",
            "CPUID.01H:ECX.XSAVE[26] = 1 → supports XGETBV/XRSTOR/XSAVE/XSETBV and CPUID.0DH",
            "CPUID.0DH sub-leaf 00H → user state bitmap (EDX:EAX), XSAVE area size (all components: ECX; current XCR0 bits: EBX)",
            "CPUID.0DH sub-leaf 01H: EAX[0] = XSAVEOPT support; EAX[1] = compaction extensions"
          ],
          "source_pages": [
            323
          ],
          "children": [
            "leaf-323"
          ],
          "score": 0.6700434684753418
        },
        {
          "id": "leaf-364",
          "level": 0,
          "summary": "Describes the recommended process for detecting Intel® AVX instructions, including pseudocode for a supports_AVX() function. The process involves using CPUID to check OSXSAVE and AVX feature flags in ECX; if set, XGETBV (with ECX=0) is used to verify the operating system has enabled XMM and YMM state support by checking EAX after AND with 06H. A note warns against relying exclusively on CPUID.01H:ECX.AVX[28] or XSAVE[26], as these indicate hardware support only, not operating system support; without OS-enabled YMM state management, Intel AVX instructions will cause #UD. These steps also apply to enhanced 128-bit SIMD floating-point instructions in Intel AVX (using VEX prefix-encoding) operating on YMM states.",
          "key_terms": [
            "Intel® AVX",
            "detection process",
            "pseudocode",
            "supports_AVX()",
            "CPUID",
            "OSXSAVE",
            "AVX feature flags",
            "ECX",
            "XGETBV",
            "XMM state",
            "YMM state",
            "OS support",
            "hardware support",
            "#UD",
            "enhanced 128-bit SIMD floating-point instructions",
            "VEX prefix-encoding"
          ],
          "source_pages": [
            364
          ],
          "children": [],
          "text_preview": "PROGRAMMING WITH INTEL® AVX, FMA, AND INTEL® AVX2\n\n\nThe following pseudocode illustrates this recommended application Intel AVX detection process:\n\nExample 14-1. Detection of Intel® AVX Instruction\n\nINT supports_AVX()\n{ mov        eax, 1\n   cpuid\n   and       ecx, 018000000H\n   cmp       ecx, 018000000H; check both OSXSAVE and AVX feature flags\n    jne      not_supported\n   ; processor supports AVX instructions and XGETBV is enabled by OS\n   mov       ecx, 0; specify 0 for XCR0 register\n   XGETBV              ; result in EDX:EAX\n   and       eax, 06H\n   cmp       eax, 06H; check OS has enabled both XMM and YMM state support\n   jne       not_supported\n   mov       eax, 1\n   jmp       done\nNOT_SUPPORTED:\n   mov       eax, 0\n   done:\n}\n\n\n                                                          NOTE\n         It is unwise for an application to rely exclusively on CPUID.01H:ECX.AVX[28] or at all on\n         CPUID.01H:ECX.XSAVE[26]: These indicate hardware support but not operating system support. If\n         YMM state management is not enabled by an operating systems, Intel AVX instructions will #UD\n         regardless of CPUID.01H:ECX.AVX[28]. “CPUID.01H:ECX.XSAVE[26] = 1” does not gua",
          "score": 0.5106192827224731
        },
        {
          "id": "leaf-365",
          "level": 0,
          "summary": "This section covers detection sequences for VEX-encoded AES instructions (e.g., VAESDEC, VAESDECLAST, VAESENC, VAESENCLAST, VAESIMC, VAESKEYGENASSIST) and VPCLMULQDQ instructions. Detection of VEX-encoded AES instructions requires checking CPUID.01H:ECX.AES[25] = 1 and application support for Intel AVX, as demonstrated in Example 14-2, which includes CPUID checks for OSXSAVE, AVX, and AESNI feature flags, and using XGETBV to verify OS-enabled XMM and YMM state support. Similarly, detection of VEX-encoded VPCLMULQDQ requires checking CPUID.01H:ECX.PCLMULQDQ[1] = 1 and AVX support, shown in Example 14-3 with CPUID checks for OSXSAVE, AVX, and PCLMULQDQ feature flags, and XGETBV to confirm OS-enabled XMM and YMM state support.",
          "key_terms": [
            "VEX-encoded AES",
            "VPCLMULQDQ",
            "VAESDEC",
            "VAESDECLAST",
            "VAESENC",
            "VAESENCLAST",
            "VAESIMC",
            "VAESKEYGENASSIST",
            "YMM states",
            "CPUID",
            "Intel AVX",
            "XGETBV",
            "XMM states",
            "AESNI feature flag",
            "PCLMULQDQ feature flag",
            "XCR0 register",
            "OSXSAVE"
          ],
          "source_pages": [
            365
          ],
          "children": [],
          "text_preview": "PROGRAMMING WITH INTEL® AVX, FMA, AND INTEL® AVX2\n\n\n\n14.3.1      Detection of VEX-Encoded AES and VPCLMULQDQ\nThe VAESDEC/VAESDECLAST/VAESENC/VAESENCLAST/VAESIMC/VAESKEYGENASSIST instructions operate on\nYMM states. The detection sequence must combine checking for CPUID.01H:ECX.AES[25] = 1 and the sequence\nfor detection application support for Intel AVX.\n\nExample 14-2. Detection of VEX-Encoded Intel® AES-NI Instructions\n\nINT supports_VAESNI()\n{ mov        eax, 1\n   cpuid\n   and       ecx, 01A000000H\n   cmp       ecx, 01A000000H; check OSXSAVE AVX and AESNI feature flags\n    jne      not_supported\n   ; processor supports AVX and VEX-encoded AESNI and XGETBV is enabled by OS\n   mov       ecx, 0; specify 0 for XCR0 register\n   XGETBV              ; result in EDX:EAX\n   and       eax, 06H\n   cmp       eax, 06H; check OS has enabled both XMM and YMM state support\n   jne       not_supported\n   mov       eax, 1\n   jmp       done\nNOT_SUPPORTED:\n   mov       eax, 0\ndone:\n\n\nSimilarly, the detection sequence for VPCLMULQDQ must combine checking for CPUID.01H:ECX.PCLMULQDQ[1] =\n1 and the sequence for detection application support for Intel AVX.\nThis is shown in the pseudocode provided in Example",
          "score": 0.45204487442970276
        },
        {
          "id": "leaf-363",
          "level": 0,
          "summary": "The content includes a continuation of Table 14-7, which lists Legacy SIMD ISA instructions (e.g., PBLENDVB, PBLENDW, PEXTRW/B/D/Q, PINSRB/D/Q) promoted to 128-bit non-arithmetic Intel AVX instructions (VEX.256 encoding: no, VEX.128 encoding: yes) with 'VI' (Vector Integer) as the reason for not being promoted to 256-bit. Section 14.3 covers detection of Intel AVX instructions, requiring checks for OS support (CPUID.01H:ECX.OSXSAVE[27] = 1, XGETBV verifying XCR0[2:1] = '11b' for XMM/YMM state enable) and processor support (CPUID.01H:ECX.AVX[28] = 1), with a recommended sequence involving these steps.",
          "key_terms": [
            "Legacy SIMD ISA",
            "Intel AVX",
            "VEX.256 Encoding",
            "VEX.128 Encoding",
            "PBLENDVB",
            "PBLENDW",
            "PEXTRW",
            "PEXTRB",
            "PEXTRD",
            "PEXTRQ",
            "PINSRB",
            "PINSRD",
            "PINSRQ",
            "VI (Vector Integer)",
            "YMM register state",
            "XGETBV instruction",
            "XSAVE/XRSTOR",
            "CPUID.01H:ECX.OSXSAVE[27]",
            "XCR0[2:1] = '11b'",
            "CPUID.01H:ECX.AVX[28]"
          ],
          "source_pages": [
            363
          ],
          "children": [],
          "text_preview": "PROGRAMMING WITH INTEL® AVX, FMA, AND INTEL® AVX2\n\n\n       Table 14-7. Promotion of Legacy SIMD ISA to 128-Bit Non-Arithmetic Intel® AVX instruction (Contd.)\n     VEX.256            VEX.128\n                                                                Instruction                              Reason Not Promoted\n     Encoding           Encoding\n\nno                yes                  PBLENDVB, PBLENDW                                            VI\nno                yes                  PEXTRW, PEXTRB, PEXTRD, PEXTRQ                               VI\nno                yes                  PINSRB, PINSRD, PINSRQ                                       VI\n\nDescription of column “Reason not promoted”:\n•    MMX: Instructions referencing MMX registers do not support VEX.\n•    Scalar: Scalar instructions are not promoted to 256-bit.\n•    VI: “Vector Integer” instructions are not promoted to 256-bit.\n•    Note 1: MOVLPD/PS and MOVHPD/PS are not promoted to 256-bit. The equivalent functionality are provided\n     by VINSERTF128 and VEXTRACTF128 instructions as the existing instructions have no natural 256b extension\n•    Note 3: It is expected that using 128-bit INSERTPS followed by a VINSERTF1",
          "score": 0.3872782588005066
        }
      ],
      "answer": "When an XSAVE-enabled feature is not fully enabled in XCR0, its registers remain unmodified and instructions associated with the feature cause invalid-opcode exceptions (#UD) [323]. XSAVE-enabled features require XCR0 configuration; if the relevant XCR0 bits are clear, the instructions are blocked. Additionally, XSAVE is only enabled if CR4.OSXSAVE=1; if CR4.OSXSAVE=0, XCR0 bits are treated as clear, further blocking XSAVE-enabled feature instructions [323].\n\nFor AVX, this explains #UD behavior because AVX is an XSAVE-enabled feature that relies on OS management of YMM state. Detection of AVX instructions requires verifying the OS has enabled XMM and YMM state support via XCR0 (specifically XCR0[2:1] = '11b') using XGETBV. Without this OS-enabled state management (i.e., XCR0 bits not set), Intel AVX instructions will cause #UD [363, 364].",
      "query_latency_ms": 15270.248,
      "external_judge": {
        "id": "raptor:relation_xcr0_ud",
        "score": 4,
        "correct": true,
        "reason": "The answer correctly explains that when an XSAVE-enabled feature is not fully enabled in XCR0, its instructions cause invalid-opcode exceptions (#UD), and this behavior applies to AVX instructions as well, which require OS management of YMM state. The answer is consistent with the provided reference."
      }
    },
    {
      "id": "graphrag:relation_xcr0_ud",
      "method": "graphrag",
      "query_id": "relation_xcr0_ud",
      "category": "relationship-multi-hop",
      "question": "What happens when an XSAVE-enabled feature is not fully enabled in XCR0, and how does that explain AVX #UD behavior?",
      "reference": "Instructions for a feature not fully enabled in XCR0 raise invalid-opcode #UD; AVX likewise #UDs when the OS has not enabled both XMM and YMM state even if the processor advertises AVX.",
      "gold_pages": [
        323,
        364
      ],
      "retrieved_pages": [
        323,
        363,
        364,
        365
      ],
      "citation_recall": 1.0,
      "retrieval_trace": {
        "entities": [
          {
            "id": "cpuid_01h_ecx_xsave_26",
            "name": "CPUID.01H:ECX.XSAVE[26]",
            "type": "CPUID Feature Flag",
            "descriptions": [
              "Hardware support indicator for XSAVE"
            ],
            "evidence": [],
            "source_pages": [
              364
            ]
          },
          {
            "id": "cpuid_instruction",
            "name": "CPUID instruction",
            "type": "Instruction",
            "descriptions": [
              "Enumerates XSAVE support via sub-leaves (e.g., 01H, 0DH)"
            ],
            "evidence": [],
            "source_pages": [
              323
            ]
          },
          {
            "id": "cr4_osxsave_bit_18",
            "name": "CR4.OSXSAVE[bit 18]",
            "type": "Register Bit",
            "descriptions": [
              "Enables XSAVE feature set when set to 1; disables if 0"
            ],
            "evidence": [],
            "source_pages": [
              323
            ]
          },
          {
            "id": "invalid_opcode_exception_#ud",
            "name": "invalid-opcode exception (#UD)",
            "type": "Exception",
            "descriptions": [
              "Triggered by executing unenabled XSAVE feature instructions"
            ],
            "evidence": [],
            "source_pages": [
              323
            ]
          },
          {
            "id": "osxsave_feature_flag",
            "name": "OSXSAVE feature flag",
            "type": "Feature Flag",
            "descriptions": [
              "Indicates OS support for XSAVE functionality"
            ],
            "evidence": [],
            "source_pages": [
              364
            ]
          },
          {
            "id": "supports_avx",
            "name": "supports_AVX()",
            "type": "Function",
            "descriptions": [
              "Function to detect Intel AVX instruction support"
            ],
            "evidence": [],
            "source_pages": [
              364
            ]
          },
          {
            "id": "user_state_components",
            "name": "User state components",
            "type": "State Component",
            "descriptions": [
              "State elements (e.g., x87, SSE) managed or not by XSAVE"
            ],
            "evidence": [],
            "source_pages": [
              323
            ]
          },
          {
            "id": "xcr0",
            "name": "XCR0",
            "type": "Register",
            "descriptions": [
              "Controls management of XSAVE-enabled state components via bit settings",
              "Extended control register holding state enable bits"
            ],
            "evidence": [],
            "source_pages": [
              323,
              363
            ]
          },
          {
            "id": "xgetbv",
            "name": "XGETBV",
            "type": "Instruction",
            "descriptions": [
              "Instruction to check enabled state in XCR0",
              "Instruction to retrieve XCR0 register value"
            ],
            "evidence": [],
            "source_pages": [
              363,
              364
            ]
          },
          {
            "id": "xsave_enabled_features",
            "name": "XSAVE-enabled features",
            "type": "Feature",
            "descriptions": [
              "Features with user state components managed by XSAVE via XCR0"
            ],
            "evidence": [],
            "source_pages": [
              323
            ]
          },
          {
            "id": "xsave_feature_set",
            "name": "XSAVE feature set",
            "type": "Feature Set",
            "descriptions": [
              "Manages state components via XCR0 and CR4.OSXSAVE configuration"
            ],
            "evidence": [],
            "source_pages": [
              323
            ]
          },
          {
            "id": "xsaveopt_instruction",
            "name": "XSAVEOPT instruction",
            "type": "Instruction",
            "descriptions": [
              "Supported if CPUID.0DH.01H.EAX[0] = 1; else causes #UD"
            ],
            "evidence": [],
            "source_pages": [
              323
            ]
          },
          {
            "id": "ymm_register_state",
            "name": "YMM register state",
            "type": "Register State",
            "descriptions": [
              "256-bit register state used by Intel AVX instructions"
            ],
            "evidence": [],
            "source_pages": [
              363
            ]
          }
        ],
        "relationships": [
          {
            "source": "xsave_feature_set",
            "target": "cr4_osxsave_bit_18",
            "type": "Prerequisite",
            "description": "Enabled only if CR4.OSXSAVE[bit 18] is set to 1",
            "evidence_quote": "",
            "source_page": 323
          },
          {
            "source": "xcr0",
            "target": "xsave_enabled_features",
            "type": "Controls",
            "description": "Bit settings determine management of their state components",
            "evidence_quote": "",
            "source_page": 323
          },
          {
            "source": "xsave_enabled_features",
            "target": "invalid_opcode_exception_#ud",
            "type": "Causes",
            "description": "Executing unenabled instructions triggers #UD",
            "evidence_quote": "",
            "source_page": 323
          },
          {
            "source": "cpuid_instruction",
            "target": "xsave_feature_set",
            "type": "Enumerates",
            "description": "Reports support via CPUID.01H:ECX.XSAVE[26] bit",
            "evidence_quote": "",
            "source_page": 323
          },
          {
            "source": "cpuid_instruction",
            "target": "xsaveopt_instruction",
            "type": "Enumerates",
            "description": "Support indicated by CPUID.0DH.01H.EAX[0] bit",
            "evidence_quote": "",
            "source_page": 323
          },
          {
            "source": "cr4_osxsave_bit_18",
            "target": "xcr0",
            "type": "Affects",
            "description": "If 0, treats all XCR0 bits as clear for state management",
            "evidence_quote": "",
            "source_page": 323
          },
          {
            "source": "xsave_feature_set",
            "target": "user_state_components",
            "type": "Manages",
            "description": "Controls modification based on XCR0 and CR4.OSXSAVE settings",
            "evidence_quote": "",
            "source_page": 323
          },
          {
            "source": "xsave_enabled_features",
            "target": "xcr0",
            "type": "Requires",
            "description": "Need XCR0 configuration to manage their state components",
            "evidence_quote": "",
            "source_page": 323
          },
          {
            "source": "xgetbv",
            "target": "xcr0",
            "type": "Checks",
            "description": "XGETBV verifies XCR0[2:1] = '11b' for state enable",
            "evidence_quote": "",
            "source_page": 363
          },
          {
            "source": "xcr0",
            "target": "ymm_register_state",
            "type": "Enables",
            "description": "XCR0[2:1] = '11b' enables YMM register state",
            "evidence_quote": "",
            "source_page": 363
          },
          {
            "source": "supports_avx",
            "target": "osxsave_feature_flag",
            "type": "checks",
            "description": "Checks via CPUID to verify OS support",
            "evidence_quote": "",
            "source_page": 364
          },
          {
            "source": "supports_avx",
            "target": "xgetbv",
            "type": "uses instruction",
            "description": "Uses to retrieve XCR0 register value",
            "evidence_quote": "",
            "source_page": 364
          },
          {
            "source": "cpuid_01h_ecx_xsave_26",
            "target": "osxsave_feature_flag",
            "type": "does not guarantee",
            "description": "Hardware flag doesn't ensure OS XSAVE usage",
            "evidence_quote": "",
            "source_page": 364
          }
        ],
        "communities": [
          {
            "id": "community-5",
            "entity_ids": [
              "cpuid_instruction",
              "cr4_osxsave_bit_18",
              "invalid_opcode_exception_#ud",
              "user_state_components",
              "xcr0",
              "xsave_enabled_features",
              "xsave_feature_set",
              "xsaveopt_instruction",
              "ymm_register_state"
            ],
            "summary": "This graph community focuses on the XSAVE feature set, which manages user state components (e.g., YMM register state) through configuration of CR4.OSXSAVE[bit 18] and XCR0. The CPUID instruction enumerates support for the XSAVE feature set and specific instructions like XSAVEOPT. The XSAVE feature set is enabled only if CR4.OSXSAVE[bit 18] is set, which affects XCR0's state management. XCR0 controls XSAVE-enabled features via bit settings, determining which state components are managed; unenabled features trigger invalid-opcode exceptions (#UD). Additionally, XCR0 enables specific states such as YMM register state when configured appropriately.",
            "key_relationships": [
              {
                "source": "xsave_feature_set",
                "target": "cr4_osxsave_bit_18",
                "type": "Prerequisite",
                "description": "Enabled only if CR4.OSXSAVE[bit 18] is set to 1"
              },
              {
                "source": "cpuid_instruction",
                "target": "xsave_feature_set",
                "type": "Enumerates",
                "description": "Reports support via CPUID.01H:ECX.XSAVE[26] bit"
              },
              {
                "source": "cpuid_instruction",
                "target": "xsaveopt_instruction",
                "type": "Enumerates",
                "description": "Support indicated by CPUID.0DH.01H.EAX[0] bit"
              },
              {
                "source": "xcr0",
                "target": "xsave_enabled_features",
                "type": "Controls",
                "description": "Bit settings determine management of their state components"
              },
              {
                "source": "cr4_osxsave_bit_18",
                "target": "xcr0",
                "type": "Affects",
                "description": "If 0, treats all XCR0 bits as clear for state management"
              },
              {
                "source": "xsave_enabled_features",
                "target": "invalid_opcode_exception_#ud",
                "type": "Causes",
                "description": "Executing unenabled instructions triggers #UD"
              },
              {
                "source": "xcr0",
                "target": "ymm_register_state",
                "type": "Enables",
                "description": "XCR0[2:1] = '11b' enables YMM register state"
              }
            ],
            "source_pages": [
              323,
              363
            ]
          },
          {
            "id": "community-3",
            "entity_ids": [
              "avx_feature_flag",
              "cpuid_01h_ecx_aes_25_flag",
              "cpuid_01h_ecx_avx_28",
              "cpuid_01h_ecx_xsave_26",
              "intel_avx_application_support",
              "osxsave_feature_flag",
              "supports_avx",
              "vaesdec_instruction",
              "vex_encoded_aes_ni_detection_sequence",
              "xcr0_register",
              "xgetbv",
              "xgetbv_instruction",
              "xmm_ymm_state_support",
              "ymm_state"
            ],
            "summary": "This graph community focuses on detecting hardware and software support for Intel AVX instructions and VEX-encoded AES-NI instructions. Key elements include detection functions (e.g., supports_AVX()), hardware/OS feature flags (e.g., AVX, OSXSAVE), registers (XCR0), instructions (XGETBV), and detection sequences (e.g., VEX-encoded AES-NI detection). It emphasizes checking both hardware capabilities (via CPUID flags) and OS support (via XCR0 register state) to confirm enablement of SIMD states (YMM/XMM) required for these instructions.",
            "key_relationships": [
              {
                "source": "supports_avx",
                "target": [
                  "osxsave_feature_flag",
                  "avx_feature_flag",
                  "xgetbv"
                ],
                "description": "Function checks OS (OSXSAVE) and hardware (AVX) flags, and uses XGETBV to retrieve XCR0 for YMM state verification"
              },
              {
                "source": "vex_encoded_aes_ni_detection_sequence",
                "target": [
                  "cpuid_01h_ecx_aes_25_flag",
                  "intel_avx_application_support",
                  "xgetbv_instruction"
                ],
                "description": "Detection sequence requires AES hardware flag, AVX application support, and uses XGETBV to check XCR0 state"
              },
              {
                "source": "xcr0_register",
                "target": [
                  "xmm_ymm_state_support"
                ],
                "description": "Register stores state enablement status, indicating OS support for XMM/YMM states via XGETBV retrieval"
              },
              {
                "source": "vaesdec_instruction",
                "target": [
                  "vex_encoded_aes_ni_detection_sequence"
                ],
                "description": "VEX-encoded AES-NI instruction requires the detection sequence to verify support"
              },
              {
                "source": [
                  "cpuid_01h_ecx_avx_28",
                  "cpuid_01h_ecx_xsave_26"
                ],
                "target": [
                  "avx_feature_flag",
                  "osxsave_feature_flag"
                ],
                "description": "Hardware CPUID flags alone are insufficient; OS support (via OSXSAVE/XCR0) is required for full AVX/XSAVE enablement"
              }
            ],
            "source_pages": [
              363,
              364,
              365
            ]
          }
        ],
        "explicit_paths": [
          {
            "hints": [
              "XCR0",
              "#UD"
            ],
            "nodes": [
              "XCR0",
              "XSAVE-enabled features",
              "invalid-opcode exception (#UD)"
            ],
            "hops": 2,
            "edges": [
              {
                "source": "xsave_enabled_features",
                "target": "xcr0",
                "type": "Requires",
                "description": "Need XCR0 configuration to manage their state components",
                "evidence_quote": "",
                "source_page": 323
              },
              {
                "source": "xsave_enabled_features",
                "target": "invalid_opcode_exception_#ud",
                "type": "Causes",
                "description": "Executing unenabled instructions triggers #UD",
                "evidence_quote": "",
                "source_page": 323
              }
            ]
          }
        ]
      },
      "answer": "When an XSAVE-enabled feature is not fully enabled in XCR0, executing instructions associated with that feature triggers an invalid-opcode exception (#UD). XCR0 controls the management of XSAVE-enabled state components via its bit settings, and XSAVE-enabled features require XCR0 configuration to manage their state components [323]. If a feature’s state component is not enabled in XCR0, executing its instructions is considered unenabled, thus causing #UD [323].  \n\nFor AVX, the YMM register state (used by AVX instructions) is enabled only if XCR0[2:1] = '11b' [363]. If this bit configuration is not present in XCR0, the YMM state is not enabled. Since AVX instructions rely on the YMM register state, their execution when YMM is unenabled (due to incomplete XCR0 configuration) triggers the #UD exception.  \n\n[323, 363]",
      "query_latency_ms": 15148.717,
      "external_judge": {
        "id": "graphrag:relation_xcr0_ud",
        "score": 4,
        "correct": true,
        "reason": "The answer correctly states that when an XSAVE-enabled feature is not fully enabled in XCR0, executing its instructions triggers an invalid-opcode exception (#UD), and this applies to AVX instructions as well, which rely on the YMM register state enabled by XCR0 configuration. The answer is consistent with the information provided in the reference."
      }
    }
  ],
  "explicit_multi_hop_paths": [
    {
      "hints": [
        "CPUID",
        "YMM"
      ],
      "nodes": [
        "CPUID instruction",
        "XSAVE feature set",
        "CR4.OSXSAVE[bit 18]",
        "XCR0",
        "YMM register state"
      ],
      "hops": 4,
      "edges": [
        {
          "source": "cpuid_instruction",
          "target": "xsave_feature_set",
          "type": "Enumerates",
          "description": "Reports support via CPUID.01H:ECX.XSAVE[26] bit",
          "evidence_quote": "",
          "source_page": 323
        },
        {
          "source": "xsave_feature_set",
          "target": "cr4_osxsave_bit_18",
          "type": "Prerequisite",
          "description": "Enabled only if CR4.OSXSAVE[bit 18] is set to 1",
          "evidence_quote": "",
          "source_page": 323
        },
        {
          "source": "cr4_osxsave_bit_18",
          "target": "xcr0",
          "type": "Affects",
          "description": "If 0, treats all XCR0 bits as clear for state management",
          "evidence_quote": "",
          "source_page": 323
        },
        {
          "source": "xcr0",
          "target": "ymm_register_state",
          "type": "Enables",
          "description": "XCR0[2:1] = '11b' enables YMM register state",
          "evidence_quote": "",
          "source_page": 363
        }
      ]
    },
    {
      "hints": [
        "XCR0",
        "#UD"
      ],
      "nodes": [
        "XCR0",
        "XSAVE-enabled features",
        "invalid-opcode exception (#UD)"
      ],
      "hops": 2,
      "edges": [
        {
          "source": "xsave_enabled_features",
          "target": "xcr0",
          "type": "Requires",
          "description": "Need XCR0 configuration to manage their state components",
          "evidence_quote": "",
          "source_page": 323
        },
        {
          "source": "xsave_enabled_features",
          "target": "invalid_opcode_exception_#ud",
          "type": "Causes",
          "description": "Executing unenabled instructions triggers #UD",
          "evidence_quote": "",
          "source_page": 323
        }
      ]
    }
  ],
  "call_totals": {
    "ark": {
      "calls": 57,
      "usage": {
        "prompt_tokens": 90885,
        "completion_tokens": 81821,
        "total_tokens": 172706
      },
      "latency_ms": 1790878.3969999996
    },
    "moonshot": {
      "calls": 1,
      "usage": {
        "prompt_tokens": 4606,
        "completion_tokens": 1409,
        "total_tokens": 6015
      },
      "latency_ms": 20871.163
    }
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  "summary": {
    "raptor": {
      "concept-detail": {
        "n": 4,
        "mean_citation_recall": 1.0,
        "mean_judge_score": 4.0,
        "mean_query_latency_ms": 10825.52175
      },
      "relationship-multi-hop": {
        "n": 4,
        "mean_citation_recall": 0.9166666666666666,
        "mean_judge_score": 4.0,
        "mean_query_latency_ms": 16744.6045
      },
      "overall": {
        "n": 8,
        "mean_citation_recall": 0.9583333333333334,
        "mean_judge_score": 4.0,
        "mean_query_latency_ms": 13785.063125
      }
    },
    "graphrag": {
      "concept-detail": {
        "n": 4,
        "mean_citation_recall": 1.0,
        "mean_judge_score": 3.0,
        "mean_query_latency_ms": 11719.119749999998
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      "relationship-multi-hop": {
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        "mean_citation_recall": 0.9166666666666666,
        "mean_judge_score": 4.0,
        "mean_query_latency_ms": 15248.592
      },
      "overall": {
        "n": 8,
        "mean_citation_recall": 0.9583333333333334,
        "mean_judge_score": 3.5,
        "mean_query_latency_ms": 13483.855875000001
      }
    }
  },
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